Host device and system including the same

Abstract

A memory module includes a first storage module including a first module controller and a first memory unit. The first storage module is configured to receive first partial data from a host and write the first partial data to the first memory unit. A second storage module includes a second module controller and a second memory unit. The second storage module is configured to receive second partial data from the host and write the second partial data to the second memory unit. The first storage module and the second storage module are configured to connect to the host through a single host interface bus.

What is claimed is: 
     
         1 . A memory module comprising:
 a module controller;   a crossbar switch connected to the module controller via a controller channel; and   a memory unit including a plurality of memory chips, the memory unit being connected to the crossbar switch via an array channel,   wherein the module controller is configured to communicate with the memory unit via the controller channel and the array channel.   
     
     
         2 . The memory module of  claim 1 , wherein the plurality of memory chips are a plurality of nonvolatile memory chips; and
 wherein the module controller is a nonvolatile module controller.   
     
     
         3 . The memory module of  claim 2 , wherein the memory module is a solid state storage module. 
     
     
         4 . The memory module of  claim 1 , wherein the plurality of memory chips are embodied as one or more 3D flash memory elements in which a plurality of memory cells are vertically stacked. 
     
     
         5 . The memory module of  claim 2 , wherein the crossbar switch is configured to transmit chip select signals to the memory unit via the array channel such that the module controller accesses the memory unit. 
     
     
         6 . The memory module of  claim 4 , wherein the memory unit is configured to indicate a status of the memory unit to the module controller by transmitting status signals indicating a write/read operation in the memory unit. 
     
     
         7 . The memory module of  claim 5 , wherein the plurality of memory chips are configured to share data input signals transmitted from the crossbar switch; and
 wherein the plurality of memory chips are configured such that the plurality of memory chips do not share the chip select signals.   
     
     
         8 . The memory module of  claim 2 , wherein the module controller is configured to transmit a crossbar switch selection signal to the crossbar switch via the controller channel such that the module controller controls the crossbar switch. 
     
     
         9 . A memory module comprising:
 a module controller;   a crossbar switch connected to the module controller via a controller channel; and   a memory unit including a first memory package and a second memory package, the first memory package is connected to the crossbar switch via a first array channel and the second memory package is connected to the crossbar switch via a second array channel,   wherein the module controller is configured to communicate with the memory unit via the controller channel, the first array channel, and the second array channel.   
     
     
         10 . The memory module of  claim 9 , wherein the first memory package and the second memory package include a plurality of nonvolatile memory chips respectively; and
 wherein the module controller is a nonvolatile module controller.   
     
     
         11 . The memory module of  claim 10 , wherein the memory module is a solid state storage module. 
     
     
         12 . The memory module of  claim 9 , wherein the first memory package and the second memory package are embodied as one or more 3D flash memory elements in which plurality of memory cells are vertically stacked. 
     
     
         13 . The memory module of  claim 10 , wherein the crossbar switch is configured to transmit first chip selection signals to the first memory package and transmit second chip selection signals to the second memory package; and
 wherein the module controller is configured to access to the first memory package and the second memory package based on the first chip selection signals and the second chip selection signals.   
     
     
         14 . The memory module of  claim 13 , wherein the first memory package and the second memory package are configured to indicate, to the module controller, statuses of the first memory package and the second memory package by respectively transmitting first status signals and second status signals indicating write/read operations in the memory unit. 
     
     
         15 . A memory module comprising:
 a module controller;   a first crossbar switch connected to the module controller via a first controller channel;   a second crossbar switch connected to the module controller via a second controller channel;   a first group of memory chips connected to the first crossbar switch via at least one first array channel; and   a second group of memory chips connected to the second crossbar switch via at least one second array channel,   wherein the module controller is configured to communicate with the first group of memory chips and the second group of memory chips via the first controller channel, the second controller channel, the at least one first array channel and the at least one second array channel.   
     
     
         16 . The memory module of  claim 15 , wherein the first group of memory chips and the second group of memory chips include a plurality of nonvolatile memory chips; and
 wherein the module controller is a nonvolatile module controller.   
     
     
         17 . The memory module of  claim 16 , wherein the memory module is a solid state storage module. 
     
     
         18 . The memory module of  claim 15 , wherein the first group of memory chips and the second group of memory chips are embodied as one or more 3D flash memory elements in which plurality of memory cells are vertically stacked. 
     
     
         19 . The memory module of  claim 16 , wherein the module controller is configured to transmit a first crossbar switch selection signal to the first crossbar switch via the first controller channel and transmit a second crossbar switch selection signal to the second crossbar switch via the second controller channel; and
 wherein the module controller is configured to control the first crossbar switch and the second crossbar switch based on the first crossbar switch selection signal and the second crossbar switch selection signal respectively.