Method for manufacturing semiconductor device

Abstract

Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.

What is claimed is: 
     
         1 . A method for manufacturing a semiconductor device, the method comprising:
 forming a dummy gate electrode on a substrate;   forming a gate spacer on a sidewall of the dummy gate electrode;   forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end;   forming a second recess by removing the dummy gate electrode remaining after forming the first recess; and   forming a metal gate electrode by depositing a metal to fill the first and second recesses.   
     
     
         2 . The method of  claim 1 , wherein the forming a first recess includes plasma-based dry etching. 
     
     
         3 . The method of  claim 2 , wherein the plasma-based dry etching is performed in a plasma chamber in which a bias voltage applied to the substrate is substantially zero. 
     
     
         4 . The method of  claim 2 , wherein the plasma-based dry etching is performed using a combination gas of HBr, NF 3 , and Cl 2 . 
     
     
         5 . The method of  claim 1 , wherein the forming a second recess includes NH 4 OH-based wet etching. 
     
     
         6 . The method of  claim 1 , further comprising:
 etching the gate spacer so that widths of the first and second recesses gradually increase from a bottom portion to a top portion.   
     
     
         7 . A method for manufacturing a semiconductor device, the method comprising:
 forming a dummy gate electrode on a substrate;   forming a gate spacer on a sidewall of the dummy gate electrode;   forming a recess by removing the dummy gate electrode;   removing parts of the gate spacer so that a width of the recess gradually increases from a bottom portion to a top portion; and   forming a metal gate electrode by depositing a metal to fill the recess.   
     
     
         8 . The method of  claim 7 , wherein the forming a recess includes forming a first recess by removing a portion of the dummy gate electrode by dry etching, and forming a second recess by wet etching to remove the dummy gate electrode remaining after the first recess is formed. 
     
     
         9 . The method of  claim 7 , further comprising:
 forming a barrier film pattern on the substrate, wherein the dummy gate electrode is formed on the barrier film pattern.   
     
     
         10 . The method of  claim 9 , wherein the removing parts of the gate spacer is performed by plasma-based dry etching using a source gas having a higher etch selectivity to the gate spacer than to the barrier film pattern. 
     
     
         11 . The method of  claim 10 , wherein the barrier film pattern includes titanium nitride. 
     
     
         12 . The method of  claim 10 , wherein the plasma-based dry etching is performed in a plasma chamber in which a bias voltage applied to the substrate is substantially zero. 
     
     
         13 . The method of  claim 10 , wherein the plasma-based dry etching is performed using a combination of HBr, NF 3 , and Cl 2  as a source gas. 
     
     
         14 . The method of  claim 13 , wherein a slope of the gate spacer is adjusted by adjusting a composition ratio of NF 3  and HBr. 
     
     
         15 . The method of  claim 10 , wherein a slope of the gate spacer is adjusted by adjusting a duration of time in which the plasma-based dry etching is performed. 
     
     
         16 . The method of  claim 9 , further comprising:
 forming a gate insulation film pattern made of a high dielectric constant (high-k) material on the substrate, wherein the barrier film pattern is formed on the gate insulation film pattern.   
     
     
         17 . A method for manufacturing a semiconductor device, the method comprising:
 forming a dummy gate electrode and gate spacer structures on a substrate, the dummy gate electrode being between the gate spacer structures;   removing the dummy gate electrode; and   forming a metal gate electrode in a space formerly occupied by the dummy gate electrode between the gate spacer structures, the metal gate electrode having a width that flares outward with increased distance from the substrate.   
     
     
         18 . The method of  claim 17 , wherein the removing the dummy gate electrode involves plasma-based dry etching to remove an initial portion of the dummy gate electrode. 
     
     
         19 . The method of  claim 18 , wherein the removing the dummy gate electrode involves wet etching to remove a remaining portion of the dummy gate electrode, the wet etching being performed after the plasma-based dry etching. 
     
     
         20 . The method of  claim 18 , wherein the plasma-based dry etching is performed using HBr, NF 3 , and Cl 2 .