Semiconductor memory device and method of operating the same

Abstract

A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array configured to include memory cells, a peripheral circuit configured to perform an erase operation and a soft program operation and a control circuit configured to control the peripheral circuit so that the memory cells are programmed though a hot carrier injection HCI method when the soft program operation is performed.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a memory cell array configured to include memory cells;   a peripheral circuit configured to perform an erase operation and a soft program operation; and   a control circuit configured to control the peripheral circuit so that the memory cells are programmed though a hot carrier injection HCI method when the soft program operation is performed.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the peripheral circuit includes:
 a voltage provision section configured to generate an erase voltage for the erase operation in response to voltage provision section control signals outputted from the control circuit, and generate a pass voltage and a control voltage for the soft program operation; and   an X decoder configured to provide the pass voltage and the control voltage to word lines connected to the memory cells in response to a row address signal outputted from the control circuit.   
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the control circuit controls the peripheral circuit so that the memory cell array is programmed in the unit of page when the soft program operation is performed. 
     
     
         4 . The semiconductor memory device of  claim 2 , wherein the X decoder provides the control voltage to a word line connected to a memory cell adjacent to a memory cell selected as a cell to be programmed of the memory cells when the soft program operation is performed, and provides the pass voltage to word lines connected to the other memory cells except the adjacent memory cell. 
     
     
         5 . The semiconductor memory device of  claim 4 , wherein the adjacent memory cell is a memory cell adjacent to the selected memory cell in the direction of a drain select transistor. 
     
     
         6 . The semiconductor memory device of  claim 4 , wherein the adjacent memory cell is turned off according to the control voltage, and the other memory cells are channel-boosted according to the pass voltage. 
     
     
         7 . The semiconductor memory device of  claim 2 , wherein the control voltage is 0V or negative voltage. 
     
     
         8 . The semiconductor memory device of  claim 2 , wherein the peripheral circuit includes further a page buffer for performing an erase verifying operation and a soft program verifying operation by sensing potential of a bit line of the memory cell array. 
     
     
         9 . The semiconductor memory device of  claim 8 , wherein the control circuit controls the peripheral circuit so that target threshold voltage in the erase verifying operation is identical to that in the soft program verifying operation. 
     
     
         10 . The semiconductor memory device of  claim 1 , wherein the control circuit controls the peripheral circuit so that the memory cell array is programmed in the unit of page when the soft program operation is performed. 
     
     
         11 . The semiconductor memory device of  claim 1 , wherein the soft program operation is performed after the erase operation is finished, and every memory cell in the memory cell array about which a soft program operation is performed has threshold voltage distribution corresponding to erase state. 
     
     
         12 . A method of operating a semiconductor memory device, the method comprising:
 increasing threshold voltage of memory cells corresponding to erase state by performing a soft program operation after an erase operation is finished, the soft program operation using a hot carrier injection HCI method;   verifying through a soft program verifying operation whether or not the threshold voltage of the memory cells is higher than a target threshold voltage; and   performing again the soft program operation and following step in case that it is determined that the threshold voltage of the memory cells is smaller than the target threshold voltage according to the soft program verifying operation.   
     
     
         13 . The method of  claim 12 , wherein the soft program operation using the HCI method includes:
 applying a control voltage to a memory cell adjacent to a memory cell selected as a cell to be programmed of the memory cells, thereby turning off the adjacent memory cell;   boosting a channel by providing a pass voltage to memory cells not selected except the adjacent memory cell and the selected memory cell; and   injecting hot carrier in a semiconductor substrate on which the adjacent memory cell is formed into a electric charge storage layer of the selected memory cell according to electric field due to the pass voltage provided to the selected memory cell, thereby programming the selected memory cell.   
     
     
         14 . The method of  claim 13 , wherein the adjacent memory cell is a memory cell adjacent to the selected memory cell in the direction of a drain select transistor. 
     
     
         15 . The method of  claim 12 , wherein the soft program operation is performed in the unit of page. 
     
     
         16 . The method of  claim 12 , wherein the target threshold voltage is lower than 0V. 
     
     
         17 . A method of operating a semiconductor memory device, the method comprising:
 erasing memory cells by applying an erase voltage to a semiconductor substrate on which a memory cell array including the memory cells is formed;   performing an erase verifying operation about the memory cells; and   performing a soft program operation through a hot carrier injection HCI method in case that it is determined that threshold voltage of the memory cells is smaller than a target threshold voltage according to the erase verifying operation.   
     
     
         18 . The method of  claim 17 , further comprising:
 increasing the erase voltage by a step voltage in case that it is determined that one or more memory cell having the threshold voltage higher than the target threshold voltage exists according to the erase verifying operation, and then performing again the step of erasing and following steps using the increased erase voltage.   
     
     
         19 . The method of  claim 17 , wherein the soft program operation is performed in the unit of page. 
     
     
         20 . The method of  claim 18 , further comprising:
 performing a soft program verifying operation about the memory cells after the soft program operation is performed.   
     
     
         21 . The method of  claim 20 , wherein it is determined that the soft program operation is passed in case that the threshold voltage of one or more memory cell is higher than the target threshold voltage according to the soft program verifying operation, and it is determined that the soft program operation is failed in case that the threshold voltages of the memory cells are smaller than the target threshold voltage. 
     
     
         22 . The method of  claim 21 , wherein the soft program operation and following step are performed again in case that it is determined that the soft program operation is failed. 
     
     
         23 . The method of  claim 21 , wherein the memory cells about which the soft program operation is performed have threshold voltage distribution corresponding to erase state. 
     
     
         24 . A method of operating a semiconductor memory device, the method comprising:
 applying a control voltage to a memory cell adjacent to a memory cell selected as a cell to be programmed in the direction of a drain select transistor, thereby turning off the adjacent memory cell;   boosting a channel by providing a pass voltage to memory cells not selected except the adjacent memory cell and the selected memory cell; and   injecting hot carrier in a semiconductor substrate on which the adjacent memory cell is formed into a electric charge storage layer of the selected memory cell according to electric field due to the pass voltage provided to the selected memory cell, thereby programming the selected memory cell.   
     
     
         25 . The method of  claim 24 , wherein every memory cell selected as a cell to be programmed about which a soft program operation is performed has threshold voltage distribution corresponding to erase state.