Digital-to-analog converter to produce paired control signals in a power supply controller

Abstract

An controller for use in a power supply includes a variable oscillator and a digital-to-analog converter (DAC). The variable oscillator generates a switching signal to control a first switch of the power supply to regulate an output current of the power supply. The variable oscillator sets a duration of an on-time of the switching signal to be inversely proportional to a magnitude of a first analog signal. The variable oscillator also sets a switching period of the switching signal to be inversely proportional to a magnitude of a second analog signal. The digital-to-analog converter (DAC) converts binary digits into the first and second analog signals, such that a sum of the magnitude of the first analog signal and the magnitude of the second analog signal is a fixed value.

What is claimed is: 
     
         1 . A controller for use in a power supply, the controller comprising:
 a variable oscillator configured to generate a switching signal to control a first switch of the power supply to regulate an output current of the power supply, wherein the variable oscillator sets a duration of an on-time of the switching signal to be inversely proportional to a magnitude of a first analog signal received by the variable oscillator, and wherein the variable oscillator sets a switching period of the switching signal to be inversely proportional to a magnitude of a second analog signal received by the variable oscillator; and   a digital-to-analog converter (DAC) coupled to receive a plurality of logic signals, each logic signal representative of a respective binary digit, wherein the DAC is configured to convert the binary digits into the first and second analog signals, such that a sum of the magnitude of the first analog signal and the magnitude of the second analog signal is a fixed value.   
     
     
         2 . The controller of  claim 1 , wherein the DAC comprises:
 a plurality of current sources; and   a plurality of single pole double throw (SPDT) switches, wherein each SPDT switch includes a pole terminal, a first throw terminal, and a second throw terminal, wherein the pole terminal is coupled to receive current from a respective current source, the first throw terminal is coupled to provide the current to the first analog signal, and the second throw terminal is coupled to provide the current to the second analog signal.   
     
     
         3 . The controller of  claim 2 , wherein each SPDT switch is configured to couple its respective current source to provide the current to the first analog signal in response to at least one of the binary digits received by the DAC, and wherein each SPDT switch is further configured to couple its respective current source to provide the current to the second analog signal in response to a complement of the at least one binary digit. 
     
     
         4 . The controller of  claim 2 , wherein the plurality of current sources are binary-weighted current sources. 
     
     
         5 . The controller of  claim 2 , wherein each SPDT switch comprises:
 a first transistor coupled to a respective current source to provide the current to the first analog signal; and   a second transistor coupled to the respective current source to provide the current to the second analog signal.   
     
     
         6 . The controller of  claim 1 , further comprising a binary counter configured to maintain a count and to generate the plurality of logic signals representative of the count in response to a clock signal. 
     
     
         7 . The controller of  claim 6 , further comprising a response circuit coupled to the binary counter to generate the clock signal and to generate a count up signal and a count down signal in response to an output sense signal that is representative of the output current of the power supply, wherein the clock signal increments the count when the count up signal is asserted and decrements the count when the count down signal is asserted. 
     
     
         8 . The controller of  claim 1 , wherein the DAC comprises:
 a first minimum current source coupled to provide a first minimum current to the first analog signal; and   a second minimum current source coupled to provide a second minimum current to the second analog signal.   
     
     
         9 . A power supply, comprising:
 a coupled inductor ;   a first switch coupled to the coupled inductor to regulate an output current of the power supply; and   a controller coupled to the first switch, the controller comprising:
 a variable oscillator configured to generate a switching signal to control the first switch, wherein the variable oscillator sets a duration of an on-time of the switching signal to be inversely proportional to a magnitude of a first analog signal received by the variable oscillator, and wherein the variable oscillator sets a switching period of the switching signal to be inversely proportional to a magnitude of a second analog signal received by the variable oscillator; and 
 a digital-to-analog converter (DAC) coupled to receive a plurality of logic signals, each logic signal representative of a respective binary digit, wherein the DAC is configured to convert the binary digits into the first and second analog signals, such that a sum of the magnitude of the first analog signal and the magnitude of the second analog signal is a fixed value. 
   
     
     
         10 . The power supply of  claim 1 , wherein the DAC comprises:
 a plurality of current sources; and   a plurality of single pole double throw (SPDT) switches, wherein each SPDT switch includes a pole terminal, a first throw terminal, and a second throw terminal, wherein the pole terminal is coupled to receive current from a respective current source, the first throw terminal is coupled to provide the current to the first analog signal, and the second throw terminal is coupled to provide the current to the second analog signal.   
     
     
         11 . The power supply of  claim 10 , wherein each SPDT switch is configured to couple its respective current source to provide the current to the first analog signal in response to at least one of the binary digits received by the DAC, and wherein each SPDT switch is further configured to couple its respective current source to provide the current to the second analog signal in response to a complement of the at least one binary digit. 
     
     
         12 . The power supply of  claim 10 , wherein the plurality of current sources are binary-weighted current sources. 
     
     
         13 . The power supply of  claim 10 , wherein each SPDT switch comprises:
 a first transistor coupled to a respective current source to provide the current to the first analog signal; and   a second transistor coupled to the respective current source to provide the current to the second analog signal.   
     
     
         14 . The power supply of  claim 9 , further comprising a binary counter configured to maintain a count and to generate the plurality of logic signals representative of the count in response to a clock signal. 
     
     
         15 . The power supply of  claim 14 , further comprising a response circuit coupled to the binary counter to generate the clock signal and to generate a count up signal and a count down signal in response to an output sense signal that is representative of the output current of the power supply, wherein the clock signal increments the count when the count up signal is asserted and decrements the count when the count down signal is asserted. 
     
     
         16 . The power supply of  claim 9 , wherein the DAC comprises:
 a first minimum current source coupled to provide a first minimum current to the first analog signal; and   a second minimum current source coupled to provide a second minimum current to the second analog signal.   
     
     
         17 . The power supply of  claim 9 , wherein the first switch and the controller are packaged together in an integrated circuit.