US2014054719A1PendingUtilityA1

Semiconductor device with resistance circuit

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Assignee: SEIKO INSTR INCPriority: Mar 13, 2011Filed: Nov 6, 2013Published: Feb 27, 2014
Est. expiryMar 13, 2031(~4.6 yrs left)· nominal 20-yr term from priority
Inventors:Hirofumi Harada
H10D 84/817H10W 20/42H10D 84/01H10D 1/474H10D 1/47H10D 84/811H10D 99/00H01L 27/0629
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Claims

Abstract

A semiconductor device has a resistance circuit including a resistance element as a first thin film arranged on an isolation oxide film provided on a surface of a semiconductor substrate, a second thin film comprised of silicon nitride formed on the first thin film, an intermediate insulating film formed on the second thin film, a contact hole passing through the second thin film, and a metal wiring formed on the contract hole. The first thin film has a low concentration impurity region and a high concentration impurity region at each of both ends of the low concentration impurity region. The second thin film is formed on the first thin film so as to be disposed on each of the high concentration impurity regions but not on the low concentration impurity region. An insulated gate field effect transistor is provided in a region of the semiconductor substrate surrounded by the isolation oxide film.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a resistance circuit comprising a resistance element comprised of a first thin film arranged on an isolation oxide film provided on a surface of a semiconductor substrate, a second thin film comprised of silicon nitride formed on the resistance element, an intermediate insulating film formed on the second thin film, a contact hole passing through the second thin film and being provided in the intermediate insulating film at a depth reaching the first thin film, and a metal wiring formed on the contact hole; and   an insulated gate field effect transistor provided in a region of the semiconductor substrate surrounded by the isolation oxide film.   
     
     
         2 . A semiconductor device according to  claim 1 ; wherein the second thin film is formed on the first thin film and has the same shape in plan view as the resistance element formed of the first thin film. 
     
     
         3 . A semiconductor device according to  claim 1 ; wherein the second thin film is formed on the first thin film and is formed in separated regions each including the contact hole. 
     
     
         4 . A semiconductor device according to  claim 1 ; wherein the second thin film is formed on the first thin film and is formed in a region including the resistance element formed of the first thin film, the region being wider than the resistance element. 
     
     
         5 . A semiconductor device according to  claim 1 ; wherein the first thin film has a thickness of 500 Å or smaller. 
     
     
         6 . A semiconductor device according to  claim 1 ; wherein the first thin film comprises a polycrystalline silicon film containing impurities of a first conductivity type at an impurity concentration in a range of 1×10 15  atoms/cm 3  to 5×10 19  atoms/cm 3 . 
     
     
         7 . A semiconductor device according to  claim 1 ; wherein the first thin film comprises a thin film made of one of CrSi, CrSiN, CrSiO, NiCr, and TiN. 
     
     
         8 . A semiconductor device according to  claim 1 ; wherein Å the second thin film has a thickness in the range of 150 Å to 350 Å.

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