Trench devices having improved breakdown voltages and method for manufacturing same

Abstract

In one embodiment, the present invention includes a semiconductor power device. The semiconductor power device comprises a trenched gate and a trenched field region. The trenched gate is disposed vertically within a trench in a semiconductor substrate. The trenched field, region is disposed vertically within the trench and below the trenched gate. A lower portion of the trenched field region tapers to dispose an electric field.

We claim 
     
         1 . A semiconductor device, comprising:
 a substrate of semiconductor material having a top surface;   a vertical trench formed in the substrate having an opening at the top surface of the substrate;   the trench having three contiguous sections - a top section, a bottom section, and a tapered transition between the top and the bottom section;   the top section extending to the top surface and with a first trench width measured between two first opposite sidewalls of the substrate material;   the bottom section perpendicular to the top surface and with a second trench width, narrower than the first trench width, measured between two second opposite sidewalls of the substrate material;   the tapered transition section having a varying trench width between the first trench width and the second trench width;   a first section of the top section covered with a first dielectric layer of a first thickness;   a second section of the top section covered with a second dielectric layer of a second thickness thicker than the first thickness; and   the second section bridging the first section and the tapered transition section.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a first gate material filling the first section of the top trench section; and   a second gate material, electrically insulated from the first gate material, filling the second section of the top trench section.   
     
     
         3 . The semiconductor device of  claim 1 , further comprising a third dielectric layer with a third thickness greater than the first thickness, covering sidewalls of the transition section of the trench. 
     
     
         4 . The semiconductor device of  claim 1 , in which the bottom section of the trench is filling with a dielectric material. 
     
     
         5 . The semiconductor device of  claim 1 , in which the first section vertically bridges two regions of n-type semiconductor material separated by a region of p-type semiconductor material. 
     
     
         6 . The semiconductor device of  claim 5 , in which one of the two n-type regions is electrically shorted to the p-type region via a metallic element. 
     
     
         7 . The semiconductor device of  claim 2 , in which the first gate material includes polysilicon. 
     
     
         8 . The semiconductor device of  claim 2 , in which the second gate material includes polysilicon. 
     
     
         9 . The semiconductor device of  claim 1 , further comprising a third dielectric layer extending from the second dielectric layer lining sidewalls of the tapered transition section. 
     
     
         10 . The semiconductor device of  claim 8 , in which the second gate material extends into the tapered section of the trench. 
     
     
         11 . The semiconductor device of  claim 9 , in which the third dielectric layer extends into the bottom section of the trench. 
     
     
         12 . The semiconductor device of  claim 1 , in which the bottom section of the trench terminates in a n-type region of the semiconductor substrate. 
     
     
         13 . The semiconductor device of  claim 5 , in which the first dielectric layer, the two n- type semiconductor regions of, the p-type semiconductor region, and the first gate material form a MOSFET. 
     
     
         14 . The semiconductor of  claim 1 , in which the first dielectric layer is thermally grown silicon dioxide.