Programmable Logic Unit and Method for Translating and Processing Instructions Using Interpretation Registers

Abstract

An architecture for microprocessors and the like in which instructions include a type identifier, which selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions).

1 . A programmable logic unit, comprising:
 one or more programmable processing elements; and   a sequencer which is connected to decode instructions in an instruction stream using indirect reference to multiple interpretation registers, as specified by a Type ID value within said instructions, and to send commands to said processing elements accordingly.   
     
     
         2 . The unit of  claim 1 , wherein said instruction stream includes both processing instructions and also sequencing instructions. 
     
     
         3 . The unit of  claim 1 , wherein said instruction stream includes both processing instructions and also sequencing instructions, and wherein both said processing instructions and said sequencing instructions include said Type ID, and wherein said Type ID also indicates whether each instruction is a processing instruction or a sequencing instruction. 
     
     
         4 . The unit of  claim 1 , wherein said instruction stream includes both processing instructions and also sequencing instructions, and said sequencing instructions can include commands for changing the values in at least some ones of said interpretation registers. 
     
     
         5 . The unit of  claim 1 , wherein said commands are expanded by at least one said sequencer; and wherein said instruction stream includes both processing instructions and also sequencing instructions; and wherein said sequencing instructions can include set-up commands which are executed by said sequencer and not by said processing elements, including commands for changing the values in the interpretation register. 
     
     
         6 . The unit of  claim 1 , wherein said commands are expanded by at least one said sequencer; and wherein said sequencer broadcasts a single instruction stream to multiple processing elements in a SIMD configuration. 
     
     
         7 . The unit of  claim 1 , wherein each single one of said instructions specifies only a single opcode. 
     
     
         8 . The unit of  claim 1 , wherein each said processing instruction includes an index number which selects a respective portion of said interpretation registers, and wherein said sequencer expands said respective processing instruction by using said respective portion of said interpretation registers. 
     
     
         9 . A method of executing a series of processing instructions, comprising the actions of:
 a) interpreting each of the instructions with reference to a respective interpretation register which is specified in a Type ID field of ones of said instructions; and   b) executing said instructions in accordance with said step (a).   
     
     
         10 . The method of  claim 9 , wherein said instruction stream includes both processing instructions and also sequencing instructions. 
     
     
         11 . The method of  claim 9 , wherein said instruction stream includes both processing instructions and also sequencing instructions, and wherein said Type ID also indicates whether each instruction is a processing instruction or a sequencing instruction. 
     
     
         12 . The method of  claim 9 , wherein said instruction stream includes both processing instructions and also sequencing instructions, and said sequencing instructions can include commands for changing the values in at least some ones of said interpretation registers. 
     
     
         13 . The method of  claim 9 , wherein said commands are expanded by at least one sequencer; and wherein said instruction stream includes both processing instructions and also sequencing instructions; and wherein said sequencing instructions can include set-up commands which are executed by said sequencer and not by said processing elements, including commands for changing the values in the interpretation register. 
     
     
         14 . The method of  claim 9 , wherein said commands are expanded by at least one sequencer; and wherein said sequencer broadcasts a single instruction stream to multiple processing elements in a SIMD configuration. 
     
     
         15 . The method of  claim 9 , wherein said command bits of each single processing instruction specify only a single opcode. 
     
     
         16 . The method of  claim 9 , wherein each said processing instruction includes an index number which selects a respective particular portion of said interpretation register, and wherein said sequencer expands said respective processing instruction by using said respective particular portion of said interpretation register. 
     
     
         17 .- 22 . (canceled) 
     
     
         23 . A computing architecture in which:
 processing instructions in an instruction stream, each including both command bits and also a Type ID which selects among multiple interpretation registers;   some of said interpretation registers containing information for interpreting said commands differently, depending on which of said interpretation registers has been selected; and   sequencing logic which is connected to expand said commands, in combination with information stored in said interpretation registers, to thereby generate an expanded instruction which is sent to one or more processing elements.   
     
     
         24 . The architecture of  claim 23 , wherein said instruction stream includes both said processing instructions and also sequencing instructions which are executed by said sequencing logic. 
     
     
         25 . The architecture of  claim 23 , wherein said instruction stream includes both said processing instructions and also sequencing instructions, and both said processing instructions and said sequencing instructions include said Type ID, and said Type ID also indicates whether each instruction is a processing instruction or a sequencing instruction. 
     
     
         26 . The architecture of  claim 23 , wherein said instruction stream includes both said processing instructions and also sequencing instructions, and the sequencing instructions can include commands for changing the values in the interpretation register. 
     
     
         27 .- 34 . (canceled)