US2014052769A1PendingUtilityA1
Tcp/ip on-time system
Est. expiryMay 7, 2030(~3.8 yrs left)· nominal 20-yr term from priority
Inventors:Michael Mcgrady
H04L 65/00H04L 63/105
46
PatentIndex Score
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Claims
Abstract
An in-memory tuple-space is created for a primary data store or access by information content versus content location. A very-small-imprint hypervisor or other implementation of a MILS architecture is created underneath the space or other store and used for store and transport of messages and/or information. This provides scalability, performance and solves the problem of delays in development authorization in multilevel security applications.
Claims
exact text as granted — not AI-modified1 .- 2 . (canceled)
3 . A system for facilitating communication between multiple devices over a network, the system comprising:
at least one memory device configured as distributed associative memory; and at least one processing device communicatively coupled to the at least one memory device, the at least one processing device including a computer-readable medium on which are stored instructions that, when executed by the processing device, enable the processing device to implement a Multiple Independent Levels of Security (MILS) architecture, the at least one processing device configured to send and receive message data over the network.
4 . The system of claim 3 , wherein the distributed associative memory comprises a tuple space.
5 . The system of claim 3 , wherein the MILS architecture comprises a hypervisor.
6 . The system of claim 4 , wherein the tuple space comprises a Java space
7 . The system of claim 6 , wherein the tuple space comprises a GigaSpace.
8 . The system of claim 5 , wherein the hypervisor comprises a Xen hypervisor.
9 . The system of claim 3 , wherein the at least one processing device is further configured to implement a real-time operating system in sending the message data over the network.
10 . A system for facilitating communication between multiple devices over a network, the system comprising:
first and second memory devices, each said memory device configured as a distributed associative memory; and first and second processing devices respectively communicatively coupled to the first and second memory devices, the first and second processing devices each including a computer-readable medium on which are stored instructions that, when executed by the first and second processing devices, enable the first and second processing devices to implement a Multiple Independent Levels of Security (MILS) architecture, the first and second processing devices configured to send and receive message data over the network, the first and second processing devices being respectively located in first and second geographic locations, the first and second processing devices configured to communicate with one another over the network.
11 . The system of claim 10 , wherein the distributed associative memory comprises a tuple space.
12 . The system of claim 10 , wherein the MILS architecture comprises a hypervisor.
13 . The system of claim 11 , wherein the tuple space comprises a Java space
14 . The system of claim 13 , wherein the tuple space comprises a GigaSpace.
15 . The system of claim 12 , wherein the hypervisor comprises a Xen hypervisor.
16 . The system of claim 10 , wherein the first and second processing devices is further configured to implement a real-time operating system in sending the message data over the network.Join the waitlist — get patent alerts
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