Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (TSV), which penetrate through the semiconductor substrate, are exposed by the recesses. Even when the TSVs have different heights from each other or the degree of back-grinding is changed, due to a process parameters, yield of the semiconductor device is improved by reducing failure caused when a TSV is not exposed.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor substrate having a first side and a second side opposite to the first side;   recesses provided in the second side; and   a first through silicon via (TSV) exposed by the recesses and penetrating the semiconductor substrate.   
     
     
         2 . The semiconductor device of  claim 1 , the device further comprising:
 a mask pattern provided over the first side of the semiconductor substrate, wherein an upper surface of the mask pattern is level with an upper surface of the first TSV; and   a metal interconnection provided over the mask pattern and coupled to the first TSV.   
     
     
         3 . The semiconductor device of  claim 1 , the device further comprising a second TSV,
 wherein the first TSV and the second TSV are formed to have different depths from each other from the first side.   
     
     
         4 . The semiconductor device of  claim 3 , wherein each of the first TSV and the second TSV has a depth smaller than a thickness of the semiconductor substrate. 
     
     
         5 . The semiconductor device of  claim 3 , the device further comprising an insulating layer formed between the first TSV and the semiconductor substrate and between the second TSV and the semiconductor substrate. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the insulating layer includes an oxide layer. 
     
     
         7 . The semiconductor device of  claim 3 , wherein each of the first TSV and the second TSV includes any of a copper layer and a barrier metal layer. 
     
     
         8 . A method for manufacturing a semiconductor device, the method comprising:
 forming a first insulating layer over a bottom of a contact hole formed in a semiconductor substrate including a first side and a second side opposite to the first side;   forming a through silicon via (TSV) over the first insulating layer to fill the contact hole;   etching the second side of the semiconductor substrate to expose the first insulating layer; and   removing the first insulating layer to form a recess in the second side of the semiconductor substrate.   
     
     
         9 . The method of  claim 8 , wherein the forming the first insulating layer over the bottom of the contact hole includes:
 forming a mask pattern over the semiconductor substrate;   etching the semiconductor substrate using the mask pattern as an etch mask to form the contact hole; and   forming the first insulating layer over the semiconductor substrate including the contact hole.   
     
     
         10 . The method of  claim 9 , wherein the first insulating layer is formed of an oxide layer or a nitride layer. 
     
     
         11 . The method of  claim 9 , the method further comprising:
 forming a second insulating layer over the first insulating layer, the mask pattern, and the first side of the semiconductor substrate, after the forming the first insulating layer.   
     
     
         12 . The method of  claim 11 , wherein the second insulating layer is formed of an oxide layer. 
     
     
         13 . The method of  claim 9 , wherein the forming the TSV includes:
 forming a metal material over the first insulating layer and the mask pattern to fill the contact hole; and   performing a planarization etch process on the metal material to expose the mask pattern.   
     
     
         14 . The method of  claim 13 , wherein the metal material includes copper. 
     
     
         15 . The method of  claim 9 , the method further comprising, after forming the TSV:
 forming a metal interconnection coupled to the TSV, the metal interconnection being provided over the mask pattern; and   forming a passivation layer over the metal interconnection.   
     
     
         16 . The method of  claim 8 , wherein the etching the semiconductor substrate to expose the bottom of the first insulating layer includes:
 back-grinding the second side of the semiconductor substrate to expose the first insulating layer.   
     
     
         17 . The method of  claim 8 , wherein the removing the first insulating layer includes performing a dip-out process. 
     
     
         18 . The method of  claim 11 , wherein the first insulating layer is provided over the bottom surface of the contact hole, but is not provided over sidewalls of the contact hole.