Power tsvs of semiconductor device

Abstract

A semiconductor device including power TSVs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs.

What is claimed is: 
     
         1 . A semiconductor device having a chip stack structure, comprising:
 a chip power pad placed in a first region of a chip;   power through silicon vias (TSVs) coupled to the chip power pad and placed in a second region of each of a plurality of chips in the chip stack structure where no pads are disposed; and   metal lines configured to couple the chip power pad and the power TSVs.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein:
 the first region is a pad region of the chip, and   the second region of each of the plurality of chips is an active region of the respective chip.   
     
     
         3 . The semiconductor device according to  claim 2 , wherein the power TSVs are used to deliver a power source directly within the active region of each chip. 
     
     
         4 . The semiconductor device according to  claim 3 , wherein the power TSVs are coupled to circuits within the active region of each chip by metal lines in a first metal layer of each chip, the first metal layer being a different metal layer than a second metal layer of the metal lines that are used to couple the chip power pad to the power TSVs. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the chip power pad and the power TSVs are coupled at an edge of the chip power pad. 
     
     
         6 . The semiconductor device according to  claim 3 , wherein the power TSVs are coupled by dummy metal lines. 
     
     
         7 . A semiconductor device having a chip stack structure, comprising:
 a pad region having a plurality of pads including a chip power pad; and   an active region including circuitry for performing a function of is the semiconductor device, a plurality of power lines, and power through silicon vias (TSVs) coupled to the chip power pad.   
     
     
         8 . The semiconductor device according to  claim 7 , wherein the active region further comprises:
 cap regions each configured to comprise a reservoir capacitor and a cutout portion; and   dummy regions each disposed by at least one of the cap regions, each of the dummy regions comprising a plurality of dummy metal lines.   
     
     
         9 . The semiconductor device according to  claim 8 , wherein the power TSVs are coupled by the dummy metal lines. 
     
     
         10 . The semiconductor device according to  claim 8 , wherein each of the power TSVs is placed within one of the cutout portions of the cap regions. 
     
     
         11 . The semiconductor device according to  claim 7 , wherein the chip power pad and the power TSV coupled to the chip power pad have an identical voltage potential. 
     
     
         12 . The semiconductor device according to  claim 11 , wherein when the identical voltage potential is a VDD voltage potential. 
     
     
         13 . The semiconductor device according to  claim 11 , wherein when the identical voltage potential is a VSS voltage potential. 
     
     
         14 . The semiconductor device according to  claim 8 , wherein the cap region compensates for parasitic capacitance of the power TSVs to reduce power noise. 
     
     
         15 . The semiconductor device according to  claim 9 , wherein the dummy metal lines for coupling the power TSVs comprise metal lines placed on opposing sides within the dummy region. 
     
     
         16 . The semiconductor device according to  claim 7 , wherein the plurality of power lines comprises:
 a first set of power lines including a first VDD power line and a first VSS power line; and   a second set of power lines including a second VDD power line and a second VSS power line, and   wherein the active region is a region bounded by the first and second set of power lines.   
     
     
         17 . The semiconductor device according to  claim 8 , wherein at least one of the cap regions has more than one cutout portion, and each of the more than one cutout portion includes a respective power TSV disposed therein.