Semiconductor devices

Abstract

A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.

1 .- 9 . (canceled) 
     
     
         10 . A semiconductor device, comprising:
 a semiconductor pattern on a substrate;   gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another;   insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern;   a common source line contacting the substrate and protruding above the uppermost insulating interlayer;   an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer;   an additional insulating interlayer on the uppermost insulating interlayer; and   contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.   
     
     
         11 . The semiconductor device as claimed in  claim 10 , wherein the etch stop layer pattern has a spacer shape, the spacer shape being disposed on sidewalls of the semiconductor pattern and on sidewalls of the common source line wherein the common source line protrudes above the uppermost insulating interlayer. 
     
     
         12 . The semiconductor device as claimed in  claim 10 , wherein the etch stop layer pattern is disposed along the uppermost insulating interlayer, the semiconductor pattern, and the common source line. 
     
     
         13 . The semiconductor device as claimed in  claim 10 , further comprising a filling layer pattern disposed on an inside of the semiconductor pattern. 
     
     
         14 . The semiconductor device as claimed in  claim 10 , wherein the gate structures comprise a tunnel insulation layer pattern, a charge storing layer pattern, a blocking dielectric layer pattern, and control gates. 
     
     
         15 . The semiconductor device as claimed in  claim 14 , wherein the control gates extend along a direction parallel to the substrate, and a control gate at a lower level extends more than a control gate at an upper level, and wherein end portions of the control gates respectively make contact with pad contacts, the pad contacts being disposed through the upper insulating interlayer and at least one of the insulating interlayers. 
     
     
         16 .- 20 . (canceled)