US2014047172A1PendingUtilityA1

Data storage device

61
Assignee: GOOGLE INCPriority: Apr 8, 2009Filed: Oct 21, 2013Published: Feb 13, 2014
Est. expiryApr 8, 2029(~2.7 yrs left)· nominal 20-yr term from priority
Inventors:Robert S. SprinkleAndrew T. SwingAlbert T. Borchers
G06F 3/0679G06F 12/0246G06F 3/0619G06F 3/0644G06F 3/0613G06F 3/0659
61
PatentIndex Score
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Claims

Abstract

A data storage device may include a first memory board having multiple memory chips and a controller board that is arranged and configured to operably connect to the first memory board. The controller board may include an interface to a host and a controller that is arranged and configured to control command processing for multiple different types of memory chips, automatically recognize a type of the memory chips on the first memory board, receive commands from the host using the interface, and execute the commands using the memory chips.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A data storage device comprising:
 a first board comprising a plurality of single-level cell (SLC) NAND memory chips;   a second board that is operably coupled to the first board, wherein the second board comprises a field programmable gate array (FPGA) controller that is arranged and configured to control memory operations for the plurality of SLC NAND memory chips and the second board is a physically different board than the first board; and   a peripheral component interconnect express (PCIe) interface that is operably coupled to the second board and that is arranged and configured to provide an interface between a host and the FPGA controller to enable the FPGA controller to communicate directly with the host over the PCIe interface.   
     
     
         2 . The data storage device of  claim 1  wherein the PCIe express interface comprises a PCIe x4 interface. 
     
     
         3 . The data storage device of  claim 1  wherein the PCIe express interface comprises a PCIe x8 interface. 
     
     
         4 . The data storage device of  claim 1  further comprising a third board comprising a plurality of SLC NAND memory chips that is operably coupled to the second board, wherein the third board is a physically different board than the first board and the second board. 
     
     
         5 . The data storage device of  claim 4  wherein:
 the first board includes at least 12 SLC NAND memory chips; and 
 the third board includes at least 12 SLC NAND memory chips. 
 
     
     
         6 . The data storage device of  claim 4  wherein:
 the first board includes at least 24 SLC NAND memory chips; and 
 the third board includes at least 24 SLC NAND memory chips. 
 
     
     
         7 . The data storage device of  claim 1  wherein the controller is arranged and configured to automatically recognize the type of the SLC NAND memory chips on the first board upon power up of the first board and the second board. 
     
     
         8 . A data storage device comprising:
 a first board comprising a plurality of multi-level cell (MLC) NAND memory chips;   a second board that is operably coupled to the first board, wherein the second board comprises a field programmable gate array (FPGA) controller that is arranged and configured to control memory operations for the plurality of MLC NAND memory chips and the second board is a physically different board than the first board; and   a peripheral component interconnect express (PCIe) interface that is operably coupled to the second board and that is arranged and configured to provide an interface between a host and the FPGA controller to enable the FPGA controller to communicate directly with the host over the PCIe interface.   
     
     
         9 . The data storage device of  claim 8  wherein the PCIe express interface comprises a PCIe x4 interface. 
     
     
         10 . The data storage device of  claim 8  wherein the PCIe express interface comprises a PCIe x8 interface. 
     
     
         11 . The data storage device of  claim 8  further comprising a third board comprising a plurality of MLC NAND memory chips that is operably coupled to the second board, wherein the third board is a physically different board than the first board and the second board. 
     
     
         12 . The data storage device of  claim 11  wherein:
 the first board includes at least 12 MLC NAND memory chips; and 
 the third board includes at least 12 MLC NAND memory chips. 
 
     
     
         13 . The data storage device of  claim 11  wherein:
 the first board includes at least 24 MLC NAND memory chips; and 
 the third board includes at least 24 MLC NAND memory chips. 
 
     
     
         14 . The data storage device of  claim 8  wherein the controller is arranged and configured to automatically recognize the type of the MLC NAND memory chips on the first board upon power up of the first board and the second board. 
     
     
         15 . A data storage device comprising:
 a first board comprising a plurality of single-level cell (SLC) NAND memory chips manufactured by a first manufacturer;   a second board that is operably coupled to the first board, wherein the second board comprises a field programmable gate array (FPGA) controller that is arranged and configured to control memory operations for the plurality of SLC NAND memory chips and the second board is a physically different board than the first board;   a peripheral component interconnect express (PCIe) interface that is operably coupled to the second board and that is arranged and configured to provide an interface between a host and the FPGA controller to enable the FPGA controller to communicate directly with the host over the PCIe interface; and   a third board comprising a plurality of SLC NAND memory chips manufactured by a second manufacturer, wherein the second manufacturer is different than the first manufacturer and the third board is configured to replace the first board and couple to the second board when the first board is disconnected from the second board.   
     
     
         16 . The data storage device of  claim 15  wherein the PCIe express interface comprises a PCIe x4 interface. 
     
     
         17 . The data storage device of  claim 15  wherein the PCIe express interface comprises a PCIe x8 interface. 
     
     
         18 . A data storage device comprising:
 a first board comprising a plurality of multi-level cell (MLC) NAND memory chips manufactured by a first manufacturer;   a second board that is operably coupled to the first board, wherein the second board comprises a field programmable gate array (FPGA) controller that is arranged and configured to control memory operations for the plurality of MLC NAND memory chips and the second board is a physically different board than the first board;   a peripheral component interconnect express (PCIe) interface that is operably coupled to the second board and that is arranged and configured to provide an interface between a host and the FPGA controller to enable the FPGA controller to communicate directly with the host over the PCIe interface; and   a third board comprising a plurality of MLC NAND memory chips manufactured by a second manufacturer, wherein the second manufacturer is different than the first manufacturer and the third board is configured to replace the first board and couple to the second board when the first board is disconnected from the second board.   
     
     
         19 . The data storage device of  claim 18  wherein the PCIe express interface comprises a PCIe x4 interface. 
     
     
         20 . The data storage device of  claim 18  wherein the PCIe express interface comprises a PCIe x8 interface.

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