Configurable memory array

Abstract

Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode.

What is claimed is: 
     
         1 . A method of testing a memory array comprising:
 selecting a high performance mode;   activating a first word line and a second word line from a single word line control signal, wherein the first word line is coupled to a first transistor and the second word line is coupled to a second transistor, each transistor being coupled to a storage element; and   selecting a bit line and a source line coupled to a bit cell, the bit cell including the storage element and the first transistor and the second transistor.   
     
     
         2 . The method of  claim 1 , wherein selecting the high performance mode comprises:
 selecting a first input of a multiplexer, wherein the first input is coupled to the single word line control signal and an output of the multiplexer is coupled to the first word line.   
     
     
         3 . The method of  claim 2 , further comprising:
 buffering the single word line control signal via a buffer coupled to the second word line to balance a delay of the multiplexer.   
     
     
         4 . The method of  claim 1 , further comprising:
 selecting a high density mode;   decoupling the first word line from the single word line control signal;   activating the second word line using the single word line control signal; and   selecting the bit line and the source line coupled to the bit cell including the storage element and the first transistor and the second transistor.   
     
     
         5 . The method of  claim 1 , wherein the bit cell further comprises a second storage element electrically decoupled from the memory array: 
     
     
         6 . A memory array comprising:
 means for selecting a high performance mode;   means for activating a first word line and a second word line from a single word line control signal, wherein the first word line is coupled to a first transistor and the second word line is coupled to a second transistor, each transistor being coupled to a storage element; and   means for selecting a bit line and a source line coupled to a bit cell including the storage element and the first transistor and the second transistor.   
     
     
         7 . The memory array of  claim 6 , wherein the means for selecting the high performance mode comprises a multiplexer. 
     
     
         8 . The memory array of  claim 7 , further comprising:
 means for buffering the single word line control signal coupled to the second word line to balance a delay of the multiplexer.   
     
     
         9 . The memory array of  claim 6 , wherein the means for selecting the high performance mode includes means for selecting a high density mode. 
     
     
         10 . The memory array of  claim 6 , wherein the bit cell further comprises a second storage element electrically decoupled from the memory array: 
     
     
         11 . The memory array of  claim 6 , wherein the memory array is integrated in at least one semiconductor die. 
     
     
         12 . The memory array of  claim 6 , further comprising a device, selected from a group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the memory array is integrated. 
     
     
         13 . A method of testing a memory array comprising:
 step for selecting a high performance mode;   step for activating a first word line and a second word line from a single word line control signal, wherein the first word line is coupled to a first transistor and the second word line is coupled to a second transistor, each transistor being coupled to a storage element; and   step for selecting a bit line and a source line coupled to a bit cell including the storage element and the first transistor and the second transistor.   
     
     
         14 . The method of  claim 13 , wherein the step for selecting the high performance mode comprises:
 step for selecting a first input of a multiplexer, wherein the first input is coupled to the single word line control signal and an output of the multiplexer is coupled to the first word line.   
     
     
         15 . The method of  claim 14 , further comprising:
 step for buffering the single word line control signal via a buffer coupled to the second word line to balance a delay of the multiplexer.   
     
     
         16 . The method of  claim 13 , further comprising:
 step for selecting a high density mode;   step for decoupling the first word line from the single word line control signal;   step for activating the second word line using the single word line control signal; and   step for selecting the bit line and the source line coupled to the bit cell including the storage element and the first transistor and the second transistor.   
     
     
         17 . The method of  claim 13 , wherein the bit cell further comprises a second storage element electrically decoupled from the memory array: 
     
     
         18 . A method of testing a memory array comprising:
 selecting a high performance mode;   coupling at least two bit lines and at least two source lines of adjacent columns to a common bit line and a common source line, respectively; and   activating a word line coupled to a bit cell, the bit cell having at least two transistors coupled to the word line, wherein each transistor is coupled to one of the at least two source lines and a storage element, and wherein the storage element is coupled to the at least two bit lines.   
     
     
         19 . The method of  claim 18 , further comprising:
 generating a first logic signal on the at least two bit lines during a write operation; and   generating a second logic signal on the at least two source lines, wherein the second logic signal is a complementary value of the first logic signal.   
     
     
         20 . The method of  claim 18 , wherein the bit cell further comprises a second storage element electrically decoupled from the memory array: 
     
     
         21 . A method of forming a memory array, the method comprising:
 disposing a plurality of word lines in rows;   disposing a plurality of bit lines and a plurality source lines in columns substantially perpendicular to the rows;   forming a plurality of storage elements having a first subset of storage elements and a second subset of storage elements;   electrically decoupling the first subset of storage elements from the memory array; and   forming a plurality of bit cells, each bit cell being formed by coupling at least two transistors to one storage element from the second subset of storage elements, wherein the plurality of bit cells are coupled to the plurality of bit lines and source lines, and wherein each transistor is coupled to one word line.   
     
     
         22 . The method of  claim 21 , wherein electrically decoupling comprises:
 severing connections between the first subset of storage elements and adjacent bit lines.   
     
     
         23 . The method of  claim 21 , wherein electrically decoupling comprises:
 modifying at least one mask to remove metal lines that coupled the first subset of storage elements and adjacent bit lines.   
     
     
         24 . The method of  claim 21 , wherein the at least two transistors are coupled in parallel by forming metal line connections between the at least two transistors.