Input switches in sampling circuits

Abstract

A switch may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second voltage level shifter may be selectively coupled between the gate and the source during the OFF phase.

1 - 5 . (canceled) 
     
     
         6 . A switching device, comprising:
 a MOS transistor alternatively operating in an ON phase and an OFF phase, the MOS transistor including a source for receiving an input signal, a drain for connecting to a load, a gate, and a back-gate that is coupled to one of the input signal and a reference; and   a first voltage level shifter switchably coupled between the source and the gate during the ON phase,   wherein during the OFF phase, the gate is switchably coupled to one of the input signal and a second voltage level shifter.   
     
     
         7 . The switching device of  claim 6 , wherein the MOS transistor is one of an NMOS transistor and a PMOS transistor. 
     
     
         8 . The switching device of  claim 6 , wherein the MOS transistor is turned on by a voltage at the gate during the ON phase and turned off by the voltage at the gate during the OFF phase. 
     
     
         9 . The switching device of  claim 6 , wherein a voltage swing between the ON and OFF phases at the gate is substantially independent from the input signal. 
     
     
         10 - 17 . (canceled) 
     
     
         18 . The switching device of  claim 6 , wherein the second voltage level shifter is coupled between the gate and a reference during the OFF phase. 
     
     
         19 . The switching device of  claim 18 , wherein the second voltage level shifter shifts a voltage at the gate to a level lower than a voltage at the source and lower than a voltage at the drain. 
     
     
         20 . The switching device of  claim 18 , wherein the second level shifter shifts the voltage at the gate to a level below the reference. 
     
     
         21 . The switching device of  claim 6 , wherein the first voltage level shifter is switchably coupled between the source and the gate during the ON phase via a first set of switches controlled by a first clock, and the second voltage level shifter is switchably coupled between the gate and the source during the OFF phase via a second set of switches controlled by a second clock. 
     
     
         22 . The switching device of  claim 21 , wherein the load is switchably coupled to the drain via a third switch controlled by a third clock. 
     
     
         23 . The switching device of  claim 22 , wherein the first, second, and third clocks are different clocks. 
     
     
         24 . The switching device of  claim 21 , wherein a phase of the first clock is opposite to a phase of the second clock. 
     
     
         25 . The switching device of  claim 21 , wherein a phase of the first clock is opposite to a phase of the second clock with an offset. 
     
     
         26 . The switching device of  claim 6 , wherein the first voltage level shifter is switchably coupled between the source and the gate during the ON phase via a first set of switches controlled by a first clock, and the gate is switchably coupled to the input signal via a second set of switches controlled by a second clock. 
     
     
         27 . The switching device of  claim 26 , wherein the load is switchably coupled to the drain via a third switch controlled by a third clock. 
     
     
         28 . The switching device of  claim 27 , wherein the first, second, and third clocks are different clocks. 
     
     
         29 . The switching device of  claim 26 , wherein a phase of the first clock is opposite to a phase of the second clock. 
     
     
         30 . The switching device of  claim 26 , wherein a phase of the first clock is opposite to a phase of the second clock with an offset. 
     
     
         31 . The switching device of  claim 6 , wherein the back-gate tracks the input signal so that the MOS transistor operates in the OFF phase. 
     
     
         32 . The switching device of  claim 6 , wherein the back-gate is coupled to the reference. 
     
     
         33 . A switching device, comprising:
 switching means for alternatively operating in an ON phase and an OFF phase, wherein the switching means includes a source for receiving an input signal, a drain for connecting to a load, a gate, and a back-gate that is coupled to one of the input signal and a reference,   first voltage level shifting means for switchably connecting the source and the gate during the ON phase,   wherein during the OFF phase, the gate is switchably coupled to one of the input signal and a second voltage level shifting means.