Method of fabricating semiconductor device and the semiconductor device

Abstract

A method of fabricating a semiconductor device includes forming a plurality of mask patterns by anisotropically etching a mask-forming film until upper surfaces of core patterns are exposed. A facing pair includes a pair of the mask patterns facing the core pattern located between the paired mask patterns. The mask patterns of the facing pair have respective lower portions spaced from each other by a first distance. An adjacent pair includes a pair of mask patterns adjacent to each other with a space having no core pattern. The mask patterns of the adjacent pair have respective lower portions spaced from each other by a second distance. The mask patterns are formed so that the second distance is larger than the first distance.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device comprising:
 a semiconductor substrate;   an insulating film formed above the semiconductor substrate; and   first buried wirings and second buried wirings formed in the insulating film and extending to a first direction and arranged in a second direction crossing to the first direction,   wherein the second buried wirings have a width between both side surfaces thereof that is increased from a lower end thereof toward an upper end thereof and a width at upper surfaces thereof is larger than a width at upper surfaces of the first buried wirings.   
     
     
         22 . The device according to  claim 21 , wherein the first and second buried wirings are formed by burying a conductive film in wiring grooves with a barrier metal film being interposed therebetween, the wiring grooves being formed in the insulating film. 
     
     
         23 . The device according to  claim 21 , wherein the first and the second burred wirings are formed of copper. 
     
     
         24 . The device according to  claim 21 , wherein the first and second buried wirings are provided so that one of second buried wiring is positioned between two of the first buried wirings and so that one of first buried wiring is positioned between two of the second buried wirings. 
     
     
         25 . The device according to  claim 21 , wherein the insulating film is mainly formed of silicon oxide. 
     
     
         26 . The device according to  claim 21 , further comprising contact plugs connecting to a surface of the semiconductor substrate through the insulating film, wherein the first and second wirings are connected to the contact plugs respectively. 
     
     
         27 . The device according to  claim 21 , which is applied to a NAND nonvolatile memory device formed on the semiconductor substrate. 
     
     
         28 . The device according to  claim 26 , wherein the first and second buried wirings are bit lines. 
     
     
         29 . The device according to  claim 22 , wherein the barrier metal film is a titanium/titanium nitride (Ti/TiN) film. 
     
     
         30 . The device according to  claim 21 , further comprising an etching stopper film located between the semiconductor substrate and the insulating film, wherein the insulating film is formed on the etching stopper film. 
     
     
         31 . The device according to  claim 30 , wherein the etching stopper film is a silicon nitride film. 
     
     
         32 . The device according to  claim 21 , wherein a level of the upper surfaces of the first buried wirings is equal to a level of the upper surfaces of the second buried wirings. 
     
     
         33 . A semiconductor device comprising:
 a semiconductor substrate;   an insulating film formed above the semiconductor substrate; and   a first wiring, a second wiring, a third wiring, and a fourth wiring disposed in the insulating film and extending to a first direction, and the second wiring disposed between the first wiring and the third wiring in a second direction crossing to the first direction, and the third wiring disposed between the second wiring and the fourth wiring in the second direction,   wherein the second wiring has a width between both side surfaces thereof that is increased from a lower end thereof toward an upper end thereof, and a width of an upper surface thereof is larger than a width at an upper surface of the third wiring.   
     
     
         34 . The device according to  claim 33 , wherein the fourth wiring has a width between both side surfaces thereof that is increased from a lower end thereof toward an upper end thereof, and a width of an upper surface thereof is larger than the width at an upper surface of the third wiring. 
     
     
         35 . The device according to  claim 34 , wherein the width of an upper surface of the second wiring is larger than a width at an upper surface of the first wiring. 
     
     
         36 . The device according to  claim 33 , wherein the first, the second, the third, and the fourth wirings are formed by burying a conductive film in a wiring groove patterns with a barrier metal film being interposed therebetween, the wiring groove patterns being formed in the insulating film. 
     
     
         37 . The device according to  claim 33 , wherein the first, the second, the third, and the fourth wirings are formed of copper. 
     
     
         38 . The device according to  claim 33 , wherein the insulating film is mainly formed of silicon oxide. 
     
     
         39 . The device according to  claim 33 , further comprising contact plugs connecting to contact portions of the semiconductor substrate through the insulating film, wherein the first, the second, the third, and the fourth wirings are connected to the contact plugs respectively. 
     
     
         40 . The device according to  claim 39 , wherein the first, the second, the third, and the fourth wirings are bit lines. 
     
     
         41 . The device according to  claim 33 , wherein a level of the upper surface of the second wiring is equal to a level of the upper surface of the third wiring. 
     
     
         42 . The device according to  claim 33 , wherein a level of an upper surface of the first wiring is equal to a level of an upper surface of the fourth wiring. 
     
     
         43 . The device according to  claim 39 , wherein the contact portions are divided by element isolation insulating films, and the element isolation insulating films have a taper shape.