Semiconductor device having vertical mos transistor and method for manufacturing the semiconductor device

Abstract

A method for manufacturing a semiconductor device including a vertical MOS transistor, includes forming a trench for shallow trench isolation in a semiconductor substrate, and burying an element isolation insulating film in the trench, forming an insulating film to be a mask for forming a semiconductor pillar, in a region subjected to shallow trench isolation, etching the semiconductor substrate in the region subjected to the shallow trench isolation with the insulating film as a mask, and forming a semiconductor pillar for the vertical MOS transistor, implanting an impurity onto the semiconductor substrate, and forming a lower diffusion layer in the portion shallower than the depth of the shallow trench isolation, and forming a gate insulating film on the semiconductor substrate and the side surface of the semiconductor pillar for the vertical MOS transistor.

What is claimed is: 
     
         1 . A method for manufacturing a semiconductor device including a vertical MOS transistor, comprising:
 forming a trench for shallow trench isolation in a semiconductor substrate, and burying an element isolation insulating film in the trench;   forming an insulating film to be a mask for forming a semiconductor pillar, in a region subjected to shallow trench isolation;   etching the semiconductor substrate in the region subjected to the shallow trench isolation with said insulating film as a mask, and forming a semiconductor pillar for the vertical MOS transistor;   implanting an impurity onto the semiconductor substrate, and forming a lower diffusion layer in the portion shallower than the depth of the shallow trench isolation;   forming a gate insulating film on the semiconductor substrate and the side surface of the semiconductor pillar for the vertical MOS transistor;   depositing a gate electrode material, etching back the gate electrode material, and leaving a gate electrode on the side surface of the semiconductor pillar for the vertical MOS transistor on which the gate insulating film is formed, and leaving the gate electrode material on the side surface of the element isolation insulating film;   forming an interlayer insulating film and flattening the interlayer insulating film to the height of the mask insulating film;   removing the mask insulating film on the semiconductor pillar for the vertical MOS transistor, and forming a sidewall insulating film in an opening which is formed;   implanting an impurity via the sidewall insulating film, and forming an upper diffusion layer on the top portion of the semiconductor pillar for the vertical MOS transistor; and   forming an electrode which contacts the gate electrode material on the side surface of the element isolation insulating film.   
     
     
         2 . The method for manufacturing a semiconductor device according to  claim 1 , wherein the semiconductor pillar for said vertical MOS transistor is formed close to the region subjected to the shallow trench isolation,
 wherein said gate electrode material formed on the side surface of the element isolation insulating film is formed to be in contact with the gate electrode of said vertical MOS transistor.   
     
     
         3 . A method for manufacturing a semiconductor device according to  claim 2 , wherein, said forming an electrode is forming an electrode which contacts the gate electrode material on the side surface of the semiconductor pillar of a dummy transistor different from said vertical MOS transistor. 
     
     
         4 . The method for manufacturing a semiconductor device according to  claim 3 , wherein the semiconductor pillar for said vertical MOS transistor is formed close to the region subjected to the shallow trench isolation, or close to the semiconductor pillar for the dummy transistor, and said gate electrode material formed on the side surface of the element isolation insulating film, or a gate electrode material of said dummy transistor in contact with the gate electrode material formed on the side surface of the element isolation insulating film is formed to be in contact with the gate electrode of said vertical MOS transistor.