Phase Shift Generating Circuit

Abstract

A phase shift generation circuit has an edge detector for generating first and second edge signals indicating first and second edges of an input pulse signal. The circuit comprises a divide by N circuit that divides the frequency of a first clock signal by N. The circuit comprises a pulse counter, which receives the first edge signal and the second clock signal, and outputs a group of signals representing the number of the second clock pulses between occurrences of the first edge signal. The circuit has a first recycling timer that outputs a group of pulses as a uniformly spaced group across the period of the input pulse. The circuit also has a second recycling timer that outputs a group of pulses as a uniformly spaced group across the period of the input pulse. The first and second recycling timers are used to generate a phase shifted output pulse.

What is claimed is: 
     
         1 . A phase shift generating circuit for receiving a pulse width modulated pulse train signal having a first frequency and a first clock signal having a second frequency with the second frequency greater than the first frequency, said circuit comprising:
 an edge detection circuit for receiving the pulse train signal and the first clock signal and for outputting a leading edge signal in response to the leading edge of the pulse train signal, and a trailing edge signal in response to the trialing edge of the pulse train signal;   a circuit for receiving the first clock signal and for generating second clock signal wherein said second clock signal is the first frequency divided by an integer N;   a pulse counter for receiving the leading edge signal or the trailing edge signal and the second clock signal to store a digital number corresponding to a period of the pulse train signal;   a first timer circuit for receiving the first clock signal and the digital number and for outputting a plurality of set signals with each set signal generated from each pulse of the first clock signal and provided on a different set output line;   a second timer circuit for receiving the first clock signal and the digital number and for outputting a plurality of reset signals with each reset signal generated from each pulse of the first clock signal and provided on a different reset output line;   a plurality of storages, each storage having a set input for receiving one of said plurality of set signals and a reset input for receiving one of said plurality of reset signals, and an output;   wherein the output of said plurality of storages is a plurality of output signals with each output signal having a time phase delay with the commencement of the plurality of output signals distributed over a period of the pulse train signal.   
     
     
         2 . The phase shift generating circuit of  claim 1  wherein said leading edge signal is generated by said edge detection circuit when said pulse train signal transitions from a low signal to a high signal. 
     
     
         3 . The phase shift generating circuit of  claim 1  wherein said trailing edge signal is generated by said edge detection circuit when said pulse train signal transitions from a high signal to a low signal. 
     
     
         4 . The phase shift generating circuit of  claim 1  wherein the pulse counter receives the trailing edge signal and the second clock signal, and stores a digital number corresponding to a period of the pulse train signal. 
     
     
         5 . The phase shift generating circuit of  claim 1  further comprising:
 a first latch for storing the digital number corresponding to a period of the pulse train signal from the pulse counter, and having a first output, supplied to the first timer circuit, with said first latch triggered by said trailing edge signal. 
 
     
     
         6 . The phase shift generating circuit of  claim 1  further comprising:
 a digital clock generator for generating the first clock signal. 
 
     
     
         7 . The phase shift generating circuit of  claim 1  further comprising:
 An analog clock generator for generating the first clock signal. 
 
     
     
         8 . The phase shift generating circuit of  claim 1  further comprising:
 a plurality of digital filter circuits, with each filter circuit associated with each storage; 
 wherein each filter circuit receives a set signal and a reset signal and supplies a filtered set signal and a filtered reset signal to each storage, with each storage receiving a filtered set signal at the set input, and a filtered reset signal at the reset input. 
 
     
     
         9 . A phase shift generation system for receiving a first plurality of enabled and disabled channel signals, representative of enabled and disabled channel information, comprising;
 a digital code conversion circuit for receiving a second plurality of channel signals, wherein said second plurality of channel signals are the enabled channel signals of the first plurality, and for converting said signals to an integer signal representative of an integer number N;   a phase generating circuit for receiving a pulse width modulated pulse train signal having a first frequency and a first clock signal having a second frequency with the second frequency greater than the first frequency, and the integer signal, and for outputting N output signals;   wherein each of the plurality of N output signals has a time phase delay with the commencement of the plurality of N output signals distributed over a period of the pulse train signal; and   a pulse reassignment control circuit for receiving the first plurality of enabled and disabled channel signals, and said plurality of N output signals, and for outputting a plurality of reassigned signals M, where M is the total of the enabled and disabled signals, wherein M>N, on M wires; wherein said pulse reassignment control circuit is for routing the N outputs of the phase generating circuit to the enabled channels in the group of M wires, depending on the first plurality of enabled and disabled channel signals.   
     
     
         10 . The phase generation system of  claim 9 , wherein said phase generating circuit comprises:
 an edge detection circuit for receiving the pulse train signal and the first clock signal and for outputting a leading edge signal in response to the leading edge of the pulse train signal, and a trailing edge signal in response to the trialing edge of the pulse train signal;   a circuit for receiving the first clock signal and for generating second clock signal wherein said second clock signal is the first frequency divided by an integer N;   a pulse counter for receiving the leading edge signal or the trailing edge signal and the second clock signal to store a digital number corresponding to a period of the pulse train signal;   a first timer circuit for receiving the first clock signal and the digital number and for outputting a plurality of set signals with each set signal generated from each pulse of the first clock signal and provided on a different set output line;   a second timer circuit for receiving the first clock signal and the digital number and for outputting a plurality of reset signals with each reset signal generated from each pulse of the first clock signal and provided on a different reset output line;   a plurality of storages, each storage having a set input for receiving one of said plurality of set signals and a reset input for receiving one of said plurality of reset signals, and an output;   wherein the output of said plurality of storages is a plurality of output signals with each output signal having a time phase delay with the commencement of the plurality of output signals distributed over a period of the pulse train signal.   
     
     
         11 . The phase shift generating circuit of  claim 9  further comprising:
 a first latch for storing the digital number corresponding to a period of the pulse train signal from the pulse counter, and having a first output, supplied to the first timer circuit, with said first latch triggered by said trailing edge signal. 
 
     
     
         12 . A phase shift generating circuit for receiving a pulse width modulated pulse train signal having a first frequency and a first clock signal having a second frequency with the second frequency greater than the first frequency and for receiving a signal representative of an integer N, said circuit comprising:
 a microcontroller having executable code therein for receiving the first clock signal, a second clock signal, wherein said second clock sign is the first frequency divided by an integer N, and the pulse width modulated train signal and for generating a plurality of output signals, up to N, with each output signal having a time phase delay with the commencement of the plurality of output signals distributed over a period of the pulse train signal.   
     
     
         13 . A method of generating pulses, comprising:
 receiving a pulse width modulated signal;   receiving a clock signal;   incrementing a first counter once for every N pulses detected in the clock signal during a period of the pulse width modulated signal to generate a first counter output M, where N is an integer and M is an integer;   latching the first counter output M using a first latch to generate a first latch output using a trailing edge of the pulse width modulated signal;   latching the first latch output using a second latch to generate a second latch output using a leading edge of the pulse width modulated signal;   receiving the first latch output and the clock signal by a first timer;   receiving the second latch output and the clock signal by a second timer; and   generating a plurality of output pulses, where a trailing edge of each output pulse is generated using the first latch output and a leading edge of each output pulse is generated using the second latch output.   
     
     
         14 . The method of  claim 13 , wherein the generating step comprises:
 receiving the first latch output by a first timer;   receiving the second latch output by a second timer;   outputting a first timer pulse from the first timer once for every MTE pulses detected in the clock signal during a period of the pulse width modulated signal, where MTE is an integer equal to the first latch output; and   outputting a second timer pulse from the second timer once for every MLE pulses detected in the clock signal during a period of the pulse width modulated signal, where MLE is an integer equal to the second latch output; and   outputting a series of output pulses using the first timer pulse and the second timer pulse.   
     
     
         15 . The method of  claim 13 , wherein each output pulse is distributed to a different channel during a period of the pulse width modulated signal. 
     
     
         16 . The method of  claim 14 , wherein each output pulse is distributed to a different channel during a period of the pulse width modulated signal. 
     
     
         17 . The method of  claim 13 , wherein each channel is coupled to a light emitting diode (LED) string. 
     
     
         18 . The method of  claim 14 , wherein each channel is coupled to a light emitting diode (LED) string. 
     
     
         19 . The method of  claim 17 , further comprising performing back lighting of a display panel using the light emitting diode (LED) strings. 
     
     
         20 . The method of  claim 18 , further comprising performing back lighting of a display panel using the light emitting diode (LED) strings.