Multilevel interconnect structures and methods of fabricating same

Abstract

A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via.

What is claimed is: 
     
         1 . A method for fabricating a multilevel interconnect structure with a first conducting level and a second conducting level, comprising:
 depositing a first dielectric layer by high density plasma deposition over a metal region;   depositing a second dielectric layer by high density plasma deposition over the first dielectric layer; and   forming a first funnel-shaped opening extending through the first dielectric layer and the second dielectric layer to reach the metal region, the first funnel-shaped opening having a first wide portion with a first sidewall opened through both the first dielectric layer and the second dielectric layer and a first narrow portion with a second sidewall opened solely through the first dielectric layer.   
     
     
         2 . The method of  claim 1 , wherein the first wide portion comprises a third sidewall opened solely through the first dielectric layer, and the first narrow portion comprises a fourth sidewall opened solely through the first dielectric layer. 
     
     
         3 . The method of  claim 1 , further comprising filling the first funnel-shaped opening with conducting material to form a first connecting via. 
     
     
         4 . The method of  claim 1 , wherein the metal region touches a substrate level. 
     
     
         5 . The method of  claim 4 , wherein the substrate level is an intermetal dielectric level. 
     
     
         6 . The method of  claim 4 , wherein the substrate level is a pre-metallic dielectric level. 
     
     
         7 . The method of  claim 1 , wherein forming the first funnel-shaped opening comprises forming the wide portion of the funnel-shaped opening using an isotropic etch. 
     
     
         8 . The method of  claim 1 , wherein forming the first funnel-shaped opening comprises forming the narrow portion of the funnel-shaped opening using an anisotropic etch. 
     
     
         9 . The method of  claim 1 , further comprising forming a second funnel-shaped opening extending through the first dielectric layer and the second dielectric layer to reach the same metal region, the second funnel-shaped opening having a second wide portion with a third sidewall opened through both the first dielectric layer and the second dielectric layer and a second narrow portion with a fourth sidewall opened solely through the first dielectric layer. 
     
     
         10 . The method of  claim 9 , wherein the second wide portion comprises a fifth sidewall opposite the third sidewall and a sixth sidewall opposite the fourth sidewall, the fifth and sixth sidewalls opened solely through the first dielectric layer. 
     
     
         11 . The method of  claim 1 , wherein the first wide portion comprises a third sidewall opposite the first sidewall and a fourth sidewall opposite the second sidewall, the third and fourth sidewalls opened through the first dielectric layer. 
     
     
         12 . A multilevel interconnect structure for a semiconductor device, the multilevel interconnect structure comprising:
 a first dielectric layer overlying a metal region;   a second dielectric layer overlying the first dielectric layer; and   a funnel-shaped connecting via extending through the first dielectric layer and the second dielectric layer to reach the metal region, the funnel-shaped connecting via having a wide upper portion extending through both the first dielectric layer and the second dielectric layer and a narrow lower portion extending solely through the first dielectric layer.   
     
     
         13 . The multilevel interconnect structure of  claim 12 , wherein the first dielectric layer is a high density plasma deposited layer, and the second dielectric layer is a high density plasma deposited layer. 
     
     
         14 . The multilevel interconnect structure of  claim 12 , wherein first dielectric layer has a thickness ranging between 0.6 μm and 1.2 μm. 
     
     
         15 . The multilevel interconnect structure of  claim 12 , further comprising:
 a substrate level; and   an adhesive layer with opposing sides connected to the substrate level and the first dielectric layer.   
     
     
         16 . A multilevel interconnect structure for a semiconductor device, the multilevel interconnect structure comprising:
 a first dielectric layer conformally covering a conducting region;   a second dielectric layer conformally covering the first dielectric layer; and   a first funnel-shaped connecting via extending through the first dielectric layer and the second dielectric layer, the first funnel-shaped connecting via having a first wide portion with a first sidewall extending through both the first dielectric layer and the second dielectric layer and a first narrow portion with a second sidewall opened solely through the first dielectric layer, wherein the first funnel-shaped connecting via is in electrical contact with the conducting region.   
     
     
         17 . The multilevel interconnect structure of  claim 16 , further comprising:
 a substrate level; and   an adhesive layer with opposing sides connected to the substrate level and the first dielectric layer.   
     
     
         18 . The multilevel interconnect structure of  claim 16 , further comprising a second funnel-shaped connecting via extending through the first dielectric layer and the second dielectric layer, the second funnel-shaped connecting via having a second wide portion opened through both the first dielectric layer and the second dielectric layer and a second narrow portion opened solely through the first dielectric layer. 
     
     
         19 . The multilevel interconnect structure of  claim 18 , wherein the first and second funnel-shaped conducting vias are filled with conducting material. 
     
     
         20 . The multilevel interconnect structure of  claim 16 , wherein the first and second dielectric layers comprise silicon dioxide deposited by high density plasma deposition.