Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes an interlayer insulating layer having openings, contact plugs formed in lower parts of the openings, wherein the contact plugs include a first conductive layer, and bit lines formed in upper parts of the openings and coupled to the contact plugs, wherein the bit lines include a second conductive layer.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 an interlayer insulating layer having openings;   contact plugs formed in lower parts of the openings, wherein the contact plugs include a first conductive layer; and   bit lines formed in upper parts of the openings and coupled to the contact plugs, wherein the bit lines include a second conductive layer.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first conductive layer includes a tungsten layer. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the second conductive layer includes a copper layer. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the lower parts of the openings are contact holes, and the upper parts of the openings are bit line trenches. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the contact plugs and the bit lines have substantially the same widths. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the contact plugs are coupled to a contact region of a substrate or channel layers of drain selection transistors. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising:
 drain selection lines formed over a substrate; and   a contact region formed in the substrate between the drain selection lines and coupled to the contact plugs.   
     
     
         8 . The semiconductor device of  claim 1 , further comprising:
 a channel layer protruding from a substrate;   plurality of memory cells stacked along the channel layer;   at least one lower selection transistor formed under the plurality of memory cells; and   at least one upper selection transistor formed above the plurality of memory cells and coupled to one of the contact plugs.   
     
     
         9 . The semiconductor device of  claim 1 , further comprising:
 a pipe gate;   a pipe channel layer formed in the pipe gate;   first and second channel layers coupled to the pipe channel layer;   a plurality of memory cells stacked along the first and second channel layers;   at least one source selection transistor formed above the plurality of memory cells stacked along the first channel layers; and   at least one drain selection transistor formed above the plurality of memory cells stacked along the second channel layers, wherein the at least one drain selection transistor is coupled to one of the contact plugs.   
     
     
         10 . A method of manufacturing a semiconductor device, the method comprising:
 forming an interlayer insulating layer;   forming contact holes by etching the interlayer insulating layer;   forming contact plugs by filling lower portions of the contact holes with a first conductive layer;   forming bit line trenches over the contact plugs in the interlayer insulating layer; and   forming bit lines by filling the bit line trenches with a second conductive layer, wherein the bit lines are coupled to the contact plugs inside the interlayer insulating layer.   
     
     
         11 . The method of  claim 10 , wherein the forming of the contact holes comprises:
 forming an etch stop layer over the interlayer insulating layer;   forming a bit line contact mask pattern over the etch stop layer;   etching the etch stop layer by using the bit line contact mask pattern as an etch barrier;   forming a bit line mask pattern on the etch stop layer; and   forming the contact holes by etching the interlayer insulating layer by using the bit line mask pattern and the etch stop layer as an etch barrier.   
     
     
         12 . The method of  claim 11 , wherein the forming of the bit line trenches comprises:
 forming the bit line trenches by etching the etch stop layer and upper portions of the interlayer insulating layer by using the bit line mask pattern as an etch barrier; and   removing the bit line mask pattern and the etch stop layer.   
     
     
         13 . The method of  claim 12 , wherein the first conductive layer includes a tungsten layer. 
     
     
         14 . The method of  claim 12 , wherein the second conductive layers include a copper layer. 
     
     
         15 . The method of  claim 12 , wherein the etch stop layer includes a nitride layer. 
     
     
         16 . The method of  claim 12 , wherein the bit line mask pattern includes a polysilicon layer. 
     
     
         17 . The method of  claim 12 , wherein the contact holes and the bit line trenches have substantially the same widths. 
     
     
         18 . The method of  claim 12 , further comprising:
 forming drain selection lines on a substrate before the forming of the interlayer insulating layer; and   forming a contact region by doping the substrate between the drain selection lines with impurities.   
     
     
         19 . The method of  claim 12 , further comprising forming at least one lower selection transistor, a plurality of memory cells and at least one upper selection transistor stacked along a channel layer protruding from a substrate before forming the interlayer insulating layer. 
     
     
         20 . The method of  claim 12 , further comprising forming a channel layer, a plurality of memory cells, at least one source selection transistor and at least one drain selection transistor before forming the interlayer insulating layer, wherein the channel layer includes a pipe channel layer formed in a pipe gate and first and second channel layers coupled to the pipe channel layer, the plurality of memory cells are stacked along the first and second channel layers, the at least one source selection transistor is formed over the plurality of memory cells stacked along the first channel layers, and the at least one drain selection transistor is formed above the plurality of memory cells stacked along the second channel layers.