Printed circuit board and method of manufacturing printed circuit board

Abstract

Disclosed herein is a printed circuit board including a base substrate, a photosensitive insulating layer formed on an upper portion of the base substrate, and a circuit pattern formed to be buried within the photosensitive insulating film.

What is claimed is: 
     
         1 . A printed circuit board comprising:
 a base substrate;   a photosensitive insulating layer formed on an upper portion of the base substrate; and   a circuit pattern formed to be buried within the photosensitive insulating film.   
     
     
         2 . The printed circuit board as set forth in  claim 1 , wherein the photosensitive insulating layer includes a first photosensitive insulating film formed on an upper portion of the base substrate and a second photosensitive insulating film formed on an upper portion of the first photosensitive insulating film. 
     
     
         3 . The printed circuit board as set forth in  claim 2 , wherein the first photosensitive insulating film and the second photosensitive insulating have different levels of sensitivity. 
     
     
         4 . The printed circuit board as set forth in  claim 2 , wherein the first photosensitive insulating film has a lower level of sensitivity than that of the second photosensitive insulating film. 
     
     
         5 . The printed circuit board as set forth in  claim 2 , wherein the circuit pattern includes:
 a first circuit pattern formed on an upper portion of the base substrate and formed to be buried within the first photosensitive insulating film;   a first via lower portion formed on an upper portion of the first circuit pattern;   a second circuit pattern formed to be buried within the second photosensitive insulating film; and   a first via upper portion formed to be buried within the second photosensitive insulating film and formed on an upper portion of the first via lower portion.   
     
     
         6 . The printed circuit board as set forth in  claim 5 , further comprising:
 a third circuit pattern formed on at least one of an upper portion of the second photosensitive insulating film, the first via upper portion, and an upper portion of the second circuit pattern.   
     
     
         7 . The printed circuit board as set forth in  claim 6 , wherein the photosensitive insulating layer further includes a third photosensitive insulating film formed on an upper portion of the second photosensitive insulating film and formed to be buried within the third circuit pattern formed on the upper portion of the second photosensitive insulating film. 
     
     
         8 . A method of manufacturing a printed circuit board, the method comprising:
 preparing a base substrate having a first circuit pattern formed thereon;   forming a photosensitive insulating layer on an upper portion of the base substrate;   exposing and developing the photosensitive insulating layer to form a first via hole and a second circuit pattern hole; and   forming a first via and a second circuit pattern in the first via hole and the second circuit pattern hole.   
     
     
         9 . The method as set forth in  claim 8 , wherein in the forming of the photosensitive insulating layer, the photosensitive insulating layer includes a first photosensitive insulating film and a second photosensitive insulating film. 
     
     
         10 . The method as set forth in  claim 9 , wherein the first photosensitive insulating film and the second photosensitive insulating film have different levels of sensitivity. 
     
     
         11 . The method as set forth in  claim 9 , wherein the first photosensitive insulating film has a lower level of sensitivity than that of the second photosensitive insulating film. 
     
     
         12 . The method as set forth in  claim 9 , wherein the first photosensitive insulating film and the second photosensitive insulating film are formed as negative photosensitive insulating films. 
     
     
         13 . The method as set forth in  claim 12 , wherein the forming of the first via hole and the second circuit pattern hole includes:
 performing an exposing operation on a region other than regions in which the first via and the second circuit pattern are to be formed in the photosensitive insulating layer;   developing the second photosensitive insulating film to form the first via hole upper portion and the second circuit pattern hole;   performing an exposing operation on the first photosensitive insulating film exposed through the second circuit pattern hole; and   developing the first photosensitive insulating film to form a first via hole lower portion.   
     
     
         14 . The method as set forth in  claim 9 , wherein the first photosensitive insulating film and the second photosensitive insulating film are formed as positive photosensitive insulating films. 
     
     
         15 . The method as set forth in  claim 14 , wherein the forming of the first via hole and the second circuit pattern hole includes:
 exposing regions of the second photosensitive insulating film in which the first via and the second circuit pattern are to be formed;   developing the exposed second photosensitive insulating film to form the first via hole upper portion and the second circuit pattern hole;   exposing the first photosensitive insulating film exposed through the first via hole upper portion; and   developing the exposed first photosensitive insulating film to form the first via hole lower portion.   
     
     
         16 . The method as set forth in  claim 9 , further comprising:
 after the forming of the first via and the second circuit pattern, forming a third circuit pattern on at least one of an upper portion of the second photosensitive insulating film, the via upper portion, and an upper portion of the second circuit pattern.   
     
     
         17 . The method as set forth in  claim 16 , wherein the forming of the third circuit pattern includes:
 forming a plated layer on an upper portion of the second photosensitive insulating film, the first via upper portion, and an upper portion of the second circuit pattern;   forming an etching resist in a region in which the third circuit pattern is to be formed;   etching the plated layer exposed by the etching resist; and   removing the etching resist.   
     
     
         18 . The method as set forth in  claim 17 , wherein the plated layer is formed simultaneously when the first via and the second circuit pattern are formed. 
     
     
         19 . The method as set forth in  claim 16 , wherein the forming of the third circuit pattern includes:
 forming a plated resist on an upper portion of the second photosensitive insulating film and having an opening exposing the region in which the third circuit pattern is to be formed;   forming the third circuit pattern in the opening of the plated resist; and   removing the plated resist.