Split embedded dram processor

Abstract

A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks. In different embodiments, standard software can be accelerated either with or without the express knowledge of the processor.

1 .- 59 . (canceled) 
     
     
         60 . An embedded DRAM coprocessor, comprising:
 an interface adapted to couple the embedded DRAM coprocessor to an external entity;   a set of one or more functional units;   a memory configured to store instructions for the set of one or more functional units;   an embedded DRAM array; and   control logic responsive to a command sent via the interface, the control logic operative to fork and execute an execution thread in support of a multithreaded program executing on the external entity.   
     
     
         61 . The embedded DRAM coprocessor of  claim 60 , wherein the embedded DRAM array includes a plurality of DRAM banks and at least one SRAM buffer register operable to buffer a row of a DRAM bank and to allow individual data words in the row to be accessed from the at least one SRAM buffer register. 
     
     
         62 . The embedded DRAM coprocessor of  claim 61 , wherein the external entity is operable to read the at least one SRAM buffer register in a burst transfer mode. 
     
     
         63 . The embedded DRAM coprocessor of  claim 61 , wherein each of the plurality of DRAM banks is associated with a row pointer that is operative to leave a specified row precharged for a plurality of access cycles. 
     
     
         64 . The embedded DRAM coprocessor of  claim 60 , wherein the command is sent by the external entity in response to making a call to an API supported by an operating system executed on the external entity. 
     
     
         65 . An embedded DRAM coprocessor, comprising:
 an interface configured to couple the embedded DRAM coprocessor to a processor;   a set of one or more functional units;   a memory configured to store instructions for the set of one or more functional units;   an embedded DRAM array; and   control logic responsive to a command sent via the interface from the processor, the control logic operative to fork and execute an execution thread in support of a multithreaded program executing on the processor.   
     
     
         66 . The embedded DRAM coprocessor of  claim 65 , wherein the command is sent by the processor in response to making a call to an API called by a driver program executed on the processor. 
     
     
         67 . The embedded DRAM coprocessor of  claim 65 , wherein the embedded DRAM array comprises a plurality of DRAM banks coupled to at least one SRAM buffer register via a bus, wherein the bus is at least 128 bits wide. 
     
     
         68 . The embedded DRAM coprocessor of  claim 67 , wherein the processor is operable to read the at least one SRAM buffer register in a burst transfer mode. 
     
     
         69 . The embedded DRAM coprocessor of  claim 66 , wherein the embedded DRAM array comprises a plurality of DRAM banks, each of the plurality of DRAM banks being associated with a row pointer that is operative to leave a specified row precharged for a plurality of access cycles. 
     
     
         70 . The embedded DRAM coprocessor of  claim 66 , wherein the command is sent by the processor in response to making a call to an API supported by an operating system executed on the processor. 
     
     
         71 . An embedded DRAM graphics accelerator, comprising:
 an interface adapted to couple the embedded DRAM coprocessor to a processor;   a set of one or more functional units;   a memory configured to store instructions for the set of one or more functional units;   an embedded DRAM array; and   control logic responsive to a command sent via the interface from the processor, the control logic operative to fork and execute an execution thread in support of a multithreaded program executing on the processor.   
     
     
         72 . The embedded DRAM graphics accelerator of  claim 71 , wherein the set of one or more functional units is optimized for graphics processing, and wherein at least a portion of the embedded DRAM array is adapted to function as a frame buffer. 
     
     
         73 . The embedded DRAM graphics accelerator of  claim 72 , further comprising a sequential access memory port coupled to the embedded DRAM array for driving an external graphics display. 
     
     
         74 . The embedded DRAM graphics accelerator of  claim 73 , wherein the interface to the processor comprises a standardized external pin interface.