Semiconductor device and method of controlling the same

Abstract

A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V 2 from a first voltage V 1 ; and a control circuit that generates the current control signal OVDR, makes a current that is flowed by the current mirror increase by a first transition of the current control signal OVDR, and makes the current that is flowed by the current mirror decrease by a second transition of the current control signal OVDR. The control circuit includes a slew-rate processing unit that makes a second slew rate of the current control signal OVDR related to the second transition be smaller than a first slew rate of the current control signal OVDR related to the first transition.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 an operational amplifier including a first input node receiving a first voltage, a second input node receiving a second voltage, and an output node, the operational amplifier further comprising a first transistor controlling a volume of the operating current flowing through the operational amplifier by a first control signal and a second transistor controlling the volume of the operating current by a second control signal;   a driver circuit responding to a voltage on the output node to drive the second input node; and   a control circuit that generates the second control signal based on the first control signal.   
     
     
         2 . The semiconductor device of  claim 1 , wherein, the driver circuit is one of an N-type channel and a P-type channel. 
     
     
         3 . The semiconductor device of  claim 1 , wherein, the operational amplifier performs one of an on and an off control of the driver circuit such that the second voltage equals the first voltage. 
     
     
         4 . The semiconductor device of  claim 3 , wherein, the operational amplifier performs one of the on and the off control of the driver circuit in a case where the first control signal is in an active state. 
     
     
         5 . The semiconductor device of  claim 1 , wherein, a switchover of an operational state of the operational amplifier by the first control signal is performed using the first transistors and the second transistors. 
     
     
         6 . The semiconductor device of  claim 1 , wherein, the control circuit activates the second control signal at an activating time of the first control signal, and after a certain period of time has elapsed, deactivates the second control signal. 
     
     
         7 . The semiconductor device of  claim 6 , wherein, the control circuit comprises a slew rate processing unit which processes a slew rate of the second control signal upon its inactivation. 
     
     
         8 . The semiconductor device of  claim 7 , wherein, the slew rate processing unit makes the slew rate of the second control signal related to inactivation smaller than a slew rate of the second control signal related to activation. 
     
     
         9 . The semiconductor device of  claim 7 , wherein, the slew rate processing unit makes the slew rate of the second control signal upon its inactivation smaller compared to a slew rate of the first control signal upon its activation of inactivation. 
     
     
         10 . The semiconductor device of  claim 1 , further comprising:
 a target voltage generating circuit that generates the first voltage;   a peripheral circuit that operated with the second voltage as an operational power source;   a phase compensation circuit which is a serial circuit of a resistive element and a capacitive element and is connected in parallel with the peripheral circuit; and   a stand-by regulator that constantly generates the second voltage when power of the semiconductor device is on.   
     
     
         11 . The semiconductor device of  claim 10 , wherein, the target voltage generating circuit generates the first voltage by dividing a power supply voltage using a resistance. 
     
     
         12 . The semiconductor device of  claim 10 , wherein, the peripheral circuit generates an internal clock only when an output of read data is performed, and is in a sleep state when the output of read data is not performed. 
     
     
         13 . The semiconductor device of  claim 10 , wherein, the phase compensation circuit stabilizes a waveform of the second voltage.