High performance ic chip having discrete decoupling capacitors attached to its ic surface

Abstract

In the present invention, discrete decoupling capacitors are mounted on the surface of an IC chip. Since a discrete capacitor can provide the capacitance of the magnitude μF, the attached capacitors can serve as the local power reservoir to decouple the external power ground noise caused by wirebonds, packages, and other system components.

1 - 65 . (canceled) 
     
     
         66 . An integrated circuit chip comprising:
 a substrate having semiconductor devices and interconnection lines formed thereover;   a passivation layer overlying said substrate;   a discrete capacitor mounted above said passivation layer; and   one or more wirebonds electrically connected to said discrete capacitor, wherein said discrete capacitor connects to a contact pad formed in openings in said passivation layer.   
     
     
         67 . An integrated circuit comprising:
 semiconductor device structures in and on a substrate;   a plurality of levels of interconnection lines and interlevel dielectric materials overlying and connecting said semiconductor device structures wherein there is at least one contact pad connected to said interconnection lines;   a passivation layer overlying said plurality of levels of interconnection lines and interlevel dielectric materials;   wirebonds formed overlying said passivation layer and connected to said at least one contact pad;   at least one discrete decoupling capacitor mounted on a solder wettable surface over said passivation layer;   a first post-passivation dielectric layer overlying said passivation layer; and   thick metal lines formed overlying said first post-passivation dielectric layer and connected to said contact pad through openings in said first post-passivation dielectric layer and said passivation layer, wherein said at least one decoupling capacitor is connected to said wirebonds through said thick metal lines.   
     
     
         68 . The integrated circuit according to  claim 67 , wherein said first post-passivation dielectric layer comprises polyimide, BCB, a porous dielectric material, parylene, or an elastomer. 
     
     
         69 . An integrated circuit comprising:
 semiconductor device structures in and on a substrate;   a plurality of levels of interconnection lines and interlevel dielectric materials overlying and connecting said semiconductor device structures wherein there is at least one contact pad connected to said interconnection lines;   a passivation layer overlying said plurality of levels of interconnection lines and interlevel dielectric materials;   wirebonds formed overlying said passivation layer and connected to said at least one contact pad;   at least one discrete decoupling capacitor mounted on a solder wettable surface over said passivation layer;   first thick metal lines overlying said passivation layer and connected to said contact pad through openings in said passivation layer;   a first post-passivation dielectric layer overlying said first thick metal lines;   second thick metal lines formed overlying said first post-passivation dielectric layer and connected to said first thick metal lines through openings in said first post-passivation dielectric layer; and   a second post-passivation dielectric layer overlying said second thick metal lines wherein said at least one decoupling capacitor is connected to said wirebonds through said second thick metal lines.   
     
     
         70 . The integrated circuit according to  claim 69 , wherein said first and second post-passivation dielectric layers comprise polyimide, BCB, a porous dielectric material, parylene, or an elastomer.