Integrated circuit devices with bump structures that include a protection layer

Abstract

Disclosed herein is a device that includes first and second spaced-apart conductive pads positioned in a layer of insulating material, first and second under-bump metallization layers that are conductively coupled to the first and second conductive pads, respectively, and first and second spaced-apart conductive bumps that are conductively coupled to the first and second under-bump metallization layers, respectively. Additionally, the device includes, among other things, a passivation layer positioned above the layer of insulating material between the first and second spaced-apart conductive bumps, and a protective layer positioned on the passivation layer, wherein the protective layer extends between and contacts the first and second under-bump metallization layers, the material of the protective layer being one of silicon dioxide, silicon oxyfluoride (SiOF), silicon nitride (SiN), and silicone carbon nitride (SiCN).

1 .- 25 . (canceled) 
     
     
         26 . A device, comprising:
 first and second spaced-apart conductive pads positioned in a layer of insulating material;   first and second under-bump metallization layers that are conductively coupled to said first and second conductive pads, respectively;   first and second spaced-apart conductive bumps that are conductively coupled to said first and second under-bump metallization layers, respectively;   a passivation layer positioned above said layer of insulating material between said first and second spaced-apart conductive bumps; and   a protective layer positioned on said passivation layer, wherein said protective layer extends between and contacts said first and second under-bump metallization layers and comprises one of silicon dioxide, silicon oxyfluoride (SiOF), silicon nitride (SiN), and silicone carbon nitride (SiCN).   
     
     
         27 . The device of  claim 26 , wherein a portion of said passivation layer extends over and contacts a portion of each of said first and second contact pads, said passivation layer being positioned between said first and second under-bump metallization layers and said respective portions of said first and second contact pads. 
     
     
         28 . The device of  claim 26 , wherein said protective layer has a thickness in the range of approximately 20-300 nm. 
     
     
         29 . The device of  claim 26 , wherein each of said first and second gate spaced-apart conductive bumps comprise tin and at least one of silver and copper. 
     
     
         30 . The device of  claim 29 , wherein each of said first and second spaced-apart conductive pads comprise copper. 
     
     
         31 . The device of  claim 26 , wherein said passivation layer is a multi-layer passivation layer, said multi-layer passivation layer comprising:
 a first layer comprised of silicon, carbon, and nitrogen, wherein said first layer is positioned on said layer of insulating material and extends over and contacts a portion of each of said first and second contact pads;   a second layer comprised of silicon dioxide positioned on said first layer; and   a third layer comprised of silicon nitride positioned on said second layer.   
     
     
         32 . The device of  claim 31 , wherein said protective layer is positioned on said third layer. 
     
     
         33 . The device of  claim 26 , further comprising a heat-cured material layer positioned on said protective layer, said heat-cured material layer extending between and contacting said first and second under-bump metallization layers. 
     
     
         34 . The device of  claim 33 , wherein said heat-cured material layer comprises one of polyimide and polybenzoxadiaziole (PBO). 
     
     
         35 . A device, comprising:
 first and second spaced-apart conductive pads positioned in a layer of insulating material;   a first under-bump metallization layer conductively coupled to said first conductive pad;   a second under-bump metallization layer conductively coupled to said second conductive pad;   first and second spaced-apart conductive bumps that are conductively coupled to said respective first and second under-bump metallization layers;   a multi-layer passivation layer positioned above said layer of insulating material, said multi-layer passivation layer extending between and contacting each of said first and second under-bump metallization layers, wherein a bottom layer of said multi-layer passivation layer extends over and contacts portions of said first and second contact pads; and   a protective layer positioned on said top layer of said multi-layer passivation layer, said protective layer extending between and contacting each of said first and second under-bump metallization layers.   
     
     
         36 . The device of  claim 35 , wherein said protective layer comprises one of silicon dioxide, silicon oxyfluoride (SiOF), silicon nitride (SiN), and silicone carbon nitride (SiCN). 
     
     
         37 . The device of  claim 36 , wherein a thickness of said protective layer is in the range of approximately 20-300 nm. 
     
     
         38 . The device of  claim 35 , wherein said top layer of said multi-layer passivation layer comprises silicon nitride and said bottom layer of said multi-layer passivation layer comprises silicon, carbon, and nitrogen. 
     
     
         39 . The device of  claim 35 , wherein said multi-layer passivation layer comprises an intermediate layer positioned between said top and layer said bottom layer, said intermediate layer comprising silicon dioxide. 
     
     
         40 . The device of  claim 35 , wherein each of said first and second gate spaced-apart conductive bumps comprise tin and at least one of silver and copper. 
     
     
         41 . The device of  claim 35 , wherein each of said first and second spaced-apart conductive pads comprise copper. 
     
     
         42 . The device of  claim 35 , further comprising a heat-cured material layer positioned on said protective layer, said heat-cured material layer extending between and contacting said first and second under-bump metallization layers. 
     
     
         43 . The device of  claim 42 , wherein said heat-cured material layer comprises one of polyimide and polybenzoxadiaziole (PBO).