Using an interconnect bump to traverse through a passivation layer of a semiconductor die

Abstract

A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.

What is claimed is: 
     
         1 . A semiconductor die comprising:
 a first semiconductor device having a first plurality of device fingers;   a first passivation layer over the first semiconductor device; and   a first interconnect bump thermally and electrically connected to each of the first plurality of device fingers, wherein the first interconnect bump protrudes through a first opening in the first passivation layer.   
     
     
         2 . The semiconductor die of  claim 1  further comprising a second semiconductor device having a second plurality of device fingers, wherein the first interconnect bump is thermally and electrically connected to each of the second plurality of device fingers. 
     
     
         3 . The semiconductor die of  claim 1  further comprising a second interconnect bump and a second semiconductor device having a second plurality of device fingers, wherein the second interconnect bump is thermally and electrically connected to each of the second plurality of device fingers, and the second interconnect bump protrudes through a second opening in the first passivation layer. 
     
     
         4 . The semiconductor die of  claim 1  further comprising a second passivation layer over the first semiconductor device, wherein:
 the first passivation layer is over the second passivation layer; 
 the first semiconductor device has a plurality of sub-cells, wherein each of the plurality of sub-cells has a corresponding portion of the first plurality of device fingers; and 
 the second passivation layer has a plurality of openings, wherein the first interconnect bump protrudes through each of the plurality of openings. 
 
     
     
         5 . The semiconductor die of  claim 4  wherein the second passivation layer comprises Silicon Dioxide. 
     
     
         6 . The semiconductor die of  claim 4  wherein a thickness of the second passivation layer adjacent to each of the plurality of openings is between about 150 nanometers and about 5500 nanometers. 
     
     
         7 . The semiconductor die of  claim 1  wherein the first passivation layer comprises BenzoCycloButene. 
     
     
         8 . The semiconductor die of  claim 1  wherein the first interconnect bump is configured to conduct heat away from the first semiconductor device. 
     
     
         9 . The semiconductor die of  claim 1  wherein the first interconnect bump is configured to provide an electrical connection from the first semiconductor device to an external device. 
     
     
         10 . The semiconductor die of  claim 1  wherein the first interconnect bump is a flip chip bump. 
     
     
         11 . The semiconductor die of  claim 1  wherein each of the first plurality of device fingers comprises a corresponding portion of a semiconductor material and a corresponding portion of a first interconnect layer, wherein each corresponding portion of the first interconnect layer is on the corresponding portion of the semiconductor material. 
     
     
         12 . The semiconductor die of  claim 11  wherein the first interconnect layer comprises gold. 
     
     
         13 . The semiconductor die of  claim 11  wherein the semiconductor material comprises Gallium Arsenide. 
     
     
         14 . The semiconductor die of  claim 11  wherein the semiconductor material comprises N-type Gallium Arsenide. 
     
     
         15 . The semiconductor die of  claim 11  further comprising a first under bump metallization layer on the first interconnect layer, wherein the first interconnect bump is over the first under bump metallization layer. 
     
     
         16 . The semiconductor die of  claim 15  wherein the first under bump metallization layer comprises Titanium. 
     
     
         17 . The semiconductor die of  claim 15  wherein a thickness of the first under bump metallization layer is between about 500 Angstroms and about 1500 Angstroms. 
     
     
         18 . The semiconductor die of  claim 15  wherein the first interconnect bump is on the first under bump metallization layer. 
     
     
         19 . The semiconductor die of  claim 15  further comprising a second under bump metallization layer, wherein the first under bump metallization layer is on the first interconnect layer, the second under bump metallization layer is on the first under bump metallization layer, and the first interconnect bump is on the second under bump metallization layer. 
     
     
         20 . The semiconductor die of  claim 1  wherein the first semiconductor device is a transistor. 
     
     
         21 . The semiconductor die of  claim 20  wherein the transistor is a heterojunction bipolar transistor. 
     
     
         22 . The semiconductor die of  claim 20  wherein the transistor is a bipolar junction transistor. 
     
     
         23 . The semiconductor die of  claim 20  wherein an emitter of the transistor comprises the first plurality of device fingers. 
     
     
         24 . The semiconductor die of  claim 1  wherein the first interconnect bump comprises Copper. 
     
     
         25 . The semiconductor die of  claim 1  wherein a height of the first interconnect bump is between about 40 micrometers and about 100 micrometers. 
     
     
         26 . The semiconductor die of  claim 1  wherein a width of the first interconnect bump is between about 70 micrometers and about 90 micrometers, and a length of the first interconnect bump is between about 80 micrometers and about 500 micrometers. 
     
     
         27 . A method comprising:
 providing a semiconductor die, which comprises:
 a first semiconductor device having a first plurality of device fingers, wherein each of the first plurality of device fingers comprises a corresponding portion of a semiconductor material and a corresponding portion of a first interconnect layer, such that each corresponding portion of the first interconnect layer is on the corresponding portion of the semiconductor material; and 
 a first passivation layer over the first semiconductor device; and 
   forming at least one under bump metallization layer on the first interconnect layer; and   forming a first interconnect bump on the at least one under bump metallization layer, wherein the first interconnect bump protrudes through a first opening in the first passivation layer.   
     
     
         28 . A method comprising:
 providing a semiconductor die, which comprises:
 a first semiconductor device having a first plurality of device fingers; and 
 a first passivation layer over the first semiconductor device; and 
   forming a first interconnect bump, which is thermally and electrically connected to each of the first plurality of device fingers, wherein the first interconnect bump protrudes through a first opening in the first passivation layer.