Semiconductor device and a method of increasing a resistance value of an electric fuse

Abstract

Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first insulator layer;   a first trench formed in the first insulator layer;   a second trench formed in the first insulator layer;   an electric fuse which includes a first barrier metal formed on a bottom surface of the first trench and a side wall of the first trench, and a first copper metal formed on the first barrier metal and filling in the first trench, wherein the electric fuse is configured to be cut by applying a current to the electric fuse;   a first wiring which includes a second barrier metal formed on a bottom surface of the second trench and a side wall of the second trench, and a second copper metal formed on the second barrier metal and filling in the second trench;   a second insulator layer formed on the first insulator layer, the electric fuse, and the first wiring;   a third insulator layer formed on the second insulator layer;   a third trench formed in the third insulator layer;   a second wiring which is formed in the third trench;   a fourth insulator layer formed over the third insulator layer;   a fourth trench formed in the fourth insulator layer; and   a third wiring which is formed in the fourth trench;   wherein a first thickness of the first wiring is thinner than a third thickness of the third wiring, and a second thickness of the second wiring is thinner than the third thickness of the third wiring,   wherein each of a dielectric relative constant of the first and third insulator layers is 3 or less, and   wherein, in a planar view, the fuse has first and second bent portions.   
     
     
         2 . A semiconductor device according to the  claim 1 ,
 wherein a cut portion of the fuse is formed between the first and second bent portions.   
     
     
         3 . A semiconductor device according to the  claim 1 , further comprising: a first transistor which is connected to the electric fuse in series between a first power supply node and a second power supply node whose power supply voltage is lower than that of the first power supply node,
 wherein a gate voltage of the first transistor is controlled so as to control applying the electrical current to the electric fuse, thereby to control the resistance value of the electric fuse.   
     
     
         4 . A semiconductor device according to the  claim 2 , further comprising: a decision circuit which receives a signal from a connect node between the first transistor and the electric fuse, and detects whether or not the resistance value of the electric fuse becomes a predetermined value or more. 
     
     
         5 . A semiconductor device according to the  claim 1 , wherein the first thickness of the first wiring is thinner than the second thickness of the second wiring. 
     
     
         6 . A semiconductor device according to the  claim 1 , wherein a linear expansion coefficient of each of the first and second copper metals is higher than that of the first and third insulator layers, and
 wherein each of the first and second copper metals has lower melting point than a melting point of each of the first and third insulator layers.   
     
     
         7 . A semiconductor device according to the  claim 1 , wherein the first barrier metal has a higher melting point than a melting point of each of the first and second copper metals. 
     
     
         8 . A semiconductor device according to the  claim 7 , wherein a linear expansion coefficient of the first barrier metal is smaller than that of each of the first and second copper metals and is larger than that of the first and third insulator layers. 
     
     
         9 . A semiconductor device according to the  claim 8 , wherein the first barrier metal has a higher melting point than a melting point of each of the first, second and third insulator layers. 
     
     
         10 . A semiconductor device, comprising:
 a semiconductor substrate;   a gate electrode formed over the semiconductor substrate;   an interlayer dielectric covering the gate electrode;   a fine layer formed over the interlayer dielectric;   a semiglobal layer formed over the fine layer;   a global layer formed over the semiglobal layer; and   an electric fuse formed in the fine layer, wherein the electric fuse is configured to be cut by applying a current to the electric fuse, the electric fuse including a copper metal,   wherein the electric fuse is formed in a trench of a first insulator layer of the fine layer, a second insulator layer is formed on the electric fuse and the first insulator layer, and a third insulator layer is formed on the second insulator layer,   wherein each of a dielectric relative constant of the first and third insulator layers is 3 or less,   wherein a thickness of a wiring formed in the semiglobal layer is thicker than that of the electric fuse formed in the fine layer,   wherein a thickness of a wiring formed in the global layer is thicker than that of the wiring formed in the semiglobal layer, and   wherein, in a planar view, the fuse has first and second bent portions.   
     
     
         11 . A semiconductor device according to the  claim 10 ,
 wherein a cut portion of the fuse is formed between the first and second bent portions.   
     
     
         12 . A semiconductor device according to the  claim 10 , wherein a plurality of fine layer are provided, and
 wherein the copper metal has a larger linear expansion coefficient than that of the first insulator layer, and further has a lower melting point than that of the first insulator layer.