Enhanced microprocessor or microcontroller

Abstract

A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.

What is claimed is: 
     
         1 . A microprocessor or microcontroller device comprising:
 a central processing unit (CPU);   a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks; and   a plurality of special function registers and general purpose registers which may be memory-mapped to said data memory, wherein at least the following special function registers are memory-mapped to all memory banks a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and   wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from said context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.   
     
     
         2 . The device according to  claim 1 , further comprising an interrupt unit coupled with the CPU, wherein said context switch is induced by an interrupt. 
     
     
         3 . The device according to  claim 1 , wherein said context switch is software induced. 
     
     
         4 . The device according to  claim 1 , wherein the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch is saved to a plurality of additional registers. 
     
     
         5 . The device according to  claim 1 , wherein the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch is saved to a stack or additional memory. 
     
     
         6 . The device according to  claim 1 , wherein each memory bank has the following special function registers memory mapped:
 a plurality of indirect addressing mode registers which cause an indirect addressing access upon a read or write access to said first and second indirect addressing mode registers;   a first program counter register;   a status register,   a plurality of indirect memory address registers;   a bank select register,   a working register,   a program counter high latch register, and   an interrupt control register.   
     
     
         7 . The device according to  claim 6 , wherein said special function registers are mapped starting at memory bank address 0. 
     
     
         8 . The device according to  claim 7 , comprising 2 indirect addressing mode registers and 4 indirect memory address registers, wherein access to an indirect addressing mode register uses 2 concatenated indirect memory address registers of said 4 indirect memory address registers and wherein said special function registers are mapped from memory bank address 0 to 0Bh. 
     
     
         9 . The device according to  claim 1 , further comprising a program memory coupled with said CPU, wherein a bit in said indirect memory address registers indicates whether an indirect memory access is performed on said data memory or said program memory. 
     
     
         10 . A method of operating a microprocessor or microcontroller device comprising a central processing unit (CPU); a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks; a plurality of special function registers and general purpose registers, the method comprising the steps of:
 memory mapping at least the following special function registers to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch;   upon occurrence of a context switch, saving automatically the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from said context switch restoring the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.   
     
     
         11 . The method according to  claim 10 , further comprising inducing said context switch by an interrupt. 
     
     
         12 . The method according to  claim 10 , wherein said context switch is software induced. 
     
     
         13 . The method according to  claim 10 , wherein the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch is saved to a plurality of additional registers. 
     
     
         14 . The method according to  claim 10 , wherein the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch is saved to a stack or additional memory. 
     
     
         15 . The method according to  claim 10 , wherein each memory bank has the following special function registers memory mapped:
 a plurality of indirect addressing mode registers which cause an indirect addressing access upon a read or write access to said first and second indirect addressing mode registers;   a first program counter register;   a status register,   a plurality of indirect memory address registers;   a bank select register,   a working register,   a program counter high latch register, and   an interrupt control register.   
     
     
         16 . The method according to  claim 15 , wherein said special function registers are mapped starting at memory bank address 0. 
     
     
         17 . The method according to  claim 15 , using 2 indirect addressing mode registers and 4 indirect memory address registers, wherein access to an indirect addressing mode register uses 2 concatenated indirect memory address registers of said 4 indirect memory address registers and wherein said special function registers are mapped from memory bank address 0 to 0Bh. 
     
     
         18 . The method according to  claim 10 , using a program memory coupled with said CPU, wherein a bit in said indirect memory address registers indicates whether an indirect memory access is performed on said data memory or said program memory.