Stt mram magnetic tunnel junction architecture and integration

Abstract

A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) includes a first conductive interconnect communicating with at least one control device and a first electrode coupling to the first conductive interconnect through a via opening formed in a dielectric passivation barrier using a first mask. The device has an MTJ stack for storing data, coupled to the first electrode. A portion of the MTJ stack has lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode is coupled to the MTJ stack and also has a lateral dimension defined by the second mask. The first electrode and a portion of the MTJ stack are defined by a third mask. A second conductive interconnect is coupled to the second electrode and at least one other control device.

What is claimed is: 
     
         1 . A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit comprising:
 providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and a first conductive interconnect;   depositing on the substrate a first dielectric passivation barrier layer having a first contact via opening formed with a first mask pattern to expose the first conductive interconnect:   depositing over the first interlevel dielectric layer, the first conductive interconnect and the first dielectric passivation barrier layer, a first electrode layer in communication with the first conductive interconnect, a fixed magnetization layer on the first electrode layer, a tunnel barrier layer on the fixed magnetization layer, a free magnetization layer on the tunnel barrier layer, and a second electrode layer on the free magnetization layer;   patterning an MTJ stack, over the first contact via opening, with a second mask pattern, in which the MTJ stack comprises the free magnetization layer and the second electrode layer;   depositing a second dielectric passivation barrier layer around the MTJ stack, in which the second dielectric passivation barrier layer is formed to leave the second electrode layer exposed;   depositing a third electrode layer on the second dielectric passivation barrier layer in communication with the second electrode layer; and   patterning the first electrode layer, at least a portion of the fixed magnetization layer, and the second dielectric passivation barrier layer with a third mask pattern.   
     
     
         2 . The method of  claim 1 , in which patterning the MTJ stack further includes patterning the tunnel barrier layer with the second mask pattern. 
     
     
         3 . The method of  claim 1 , further comprising patterning the tunnel barrier layer with the third mask pattern. 
     
     
         4 . The method of  claim 1 , further comprising patterning the third electrode layer with the third mask pattern. 
     
     
         5 . The method of  claim 1 , further comprising fabricating a second conductive interconnect in communication with the third electrode layer. 
     
     
         6 . The method of  claim 1 , further comprising depositing a global dielectric passivation barrier layer over the third electrode layer after patterning with the third mask pattern. 
     
     
         7 . The method of  claim 6 , further comprising:
 depositing a second interlayer dielectric on the global dielectric passivation barrier layer;   planarizing the second interlayer dielectric to expose the global dielectric passivation barrier layer over the third electrode layer; and   forming a second contact via opening in the global dielectric passivation barrier layer to expose a portion of the third electrode layer.   
     
     
         8 . The method of  claim 1 , further comprising patterning a second portion of the fixed magnetization layer with the second mask pattern, 
     
     
         9 . The method of  claim 1 , in which the second mask pattern has an ellipsoid shape 
     
     
         10 . The method of  claim 1 , further comprising integrating the MTJ device into a spin torque transfer (STT) magnetic random access memory (MRAM) device. 
     
     
         11 . The method of  claim 1 , further comprising integrating the MTJ device into a semiconductor device. 
     
     
         12 . The method of  claim 1 , wherein the integrated circuit is applied in an electronic device, selected from a group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the integrated circuit is integrated. 
     
     
         13 . A magnetic tunnel junction (MTJ) structure for magnetic random access memory (MRAM) comprising:
 first interconnect means for communicating with at least one control device;   first electrode means for coupling to the first interconnect means through a contact via opening formed in a dielectric passivation barrier using a first mask;   means for magnetically storing data, the storing means coupling to the first electrode means, a lateral dimension of a portion of the storing means being defined by a second mask;   second electrode means for coupling to the storing means, the second electrode means having a same lateral dimension as the portion of the storing means defined by the second mask;   third electrode means for coupling to the second electrode means, the third electrode means, a portion of the storing means and the first electrode means having a shape based upon a third mask; and   second interconnect means for coupling to the third electrode means and at least one other control device.   
     
     
         14 . The MTJ structure of  claim 13 , in which the contact via opening is at least as wide as the first interconnect means. 
     
     
         15 . The MTJ structure of  claim 13 , in which the second mask has an ellipsoid shape. 
     
     
         16 . The MTJ structure of  claim 13 , in which a tunnel barrier layer shape of the storing means is based upon the second mask. 
     
     
         17 . The MTJ structure of  claim 13 , integrated into a spin-torque-transfer (STT) MRAM semiconductor die. 
     
     
         18 . The MTJ structure of  claim 13 , in which the MTJ structure is integrated into a device selected from a group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer. 
     
     
         19 . A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit comprising the steps of:
 providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and a first conductive interconnect;   depositing on the substrate a first dielectric passivation barrier layer having a first contact via opening formed with a first mask pattern to expose the first conductive interconnect:   depositing over the first interlevel dielectric layer, the first conductive interconnect and the first dielectric passivation harrier layer, a first electrode layer n communication with the first conductive interconnect, a fixed magnetization layer on the first electrode layer, a tunnel barrier layer on the fixed magnetization layer, a free magnetization layer on the tunnel barrier layer, and a second electrode layer on the flee magnetization layer;   patterning an MTJ stack, over the first contact via opening, with a second mask pattern, in which the MTJ stack comprises the free magnetization layer and the second electrode layer;   depositing a second dielectric passivation barrier layer around the MTJ stack, in which the second dielectric passivation barrier layer is formed to leave the second electrode layer exposed;   depositing a third electrode layer on the second dielectric passivation barrier layer in communication with the second electrode: layer; and   patterning the first electrode layer, at least a portion of the fixed magnetization layer and the second dielectric passivation barrier layer with a third mask pattern.   
     
     
         20 . The method of  claim 19 , wherein the integrated circuit is applied in an electronic device, selected from a group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the integrated circuit is integrated.