Array operation using a schottky diode as a non-ohmic selection device

Abstract

A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.

What is claimed is: 
     
         1 . A memory device, comprising:
 a re-writeable non-volatile memory element (ME) having exactly two terminals and including electrically in series with the two terminals
 a binary conductive oxide layer including mobile ions and, 
 a tunnel barrier layer having a thickness less than approximately 50 Angstroms; and 
   a selection device including a layer of metal in contact with a single layer of doped polycrystalline silicon, the contact operative to form a single Schottky diode, the Schottky diode and the ME are electrically in series with each other.   
     
     
         2 . The memory device of  claim 1 , wherein the single layer of doped polycrystalline silicon is doped n−. 
     
     
         3 . The memory device of  claim 1 , wherein the single layer of doped polycrystalline silicon includes a first portion that is doped n− and a second portion that is doped n+, the first portion is in contact with the layer of metal and the second portion is not in contact with the layer of metal. 
     
     
         4 . The memory device of  claim 3  and further comprising:
 an electrically conductive silicide layer in contact with the second portion. 
 
     
     
         5 . The memory device of  claim 4 , wherein the silicide layer comprises a nickel silicide or a cobalt silicide. 
     
     
         6 . The memory device of  claim 1 , wherein the metal layer comprises a metal selected from the group consisting of tungsten, aluminum, and platinum. 
     
     
         7 . The memory device of  claim 1 , wherein one of the layers of the selection device is in direct contact with one of the layers of the ME. 
     
     
         8 . The memory device of  claim 1 , wherein one of the two terminals is electrically coupled with a first conductive array line and another one of the two terminals is electrically coupled with a second conductive array line. 
     
     
         9 . The memory device of  claim 8 , wherein the first conductive array line comprises one of a plurality of first conductive array lines and the second conductive array line comprises one of a plurality of second conductive array lines and the plurality of first and second conductive array lines are disposed in a cross-point array. 
     
     
         10 . The memory device of  claim 9 , wherein the cross-point array is positioned above, is in contact with, and is fabricated back-end-of-the-line (BEOL) directly above a semiconductor substrate including active circuitry fabricated front-end-of-the-line (FEOL) on the semiconductor substrate and electrically coupled with the plurality of first and second conductive array lines. 
     
     
         11 . The memory device of  claim 10  and further comprising:
 a plurality of the cross-point arrays in contact with one another and vertically disposed over one another in a stacked configuration. 
 
     
     
         12 . The two-terminal memory cell of  claim 1 , wherein the ME and the selection device are positioned above and are fabricated back-end-of-the-line (BEOL) directly above a semiconductor substrate including active circuitry fabricated front-end-of-the-line (FEOL) on the semiconductor substrate and electrically coupled with the first and second terminals. 
     
     
         13 . The two-terminal memory cell of  claim 1 , wherein the ME is configured to store at least one-bit of non-volatile data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across its two terminals, the data is retained in an absence of electrical power, and the data can be reversibly switched between a programmed conductivity profile and an erased conductivity profile by applying a write voltage across the two terminals. 
     
     
         14 . The two-terminal memory cell of  claim 13 , wherein the selection device is configured to substantially block current flow through the ME for voltages other than the read voltage or the write voltage. 
     
     
         15 . A memory device, comprising:
 a re-writeable non-volatile memory element (ME) having exactly two terminals and including electrically in series with the two terminals
 a binary conductive oxide layer including mobile ions and, 
 a tunnel barrier layer having a thickness less than approximately 50 Angstroms; and 
   a selection device configured as a single Schottky diode including a single layer of an oxide semiconductor material, an ohmic metal in contact with the oxide semiconductor material, and a non-ohmic metal in contact with the oxide semiconductor material, the selection device and the ME are electrically in series with each other.   
     
     
         16 . A two-terminal memory cell, comprising:
 a re-writeable non-volatile memory element (ME) having exactly two terminals and including electrically in series with the two terminals
 a binary conductive oxide layer including mobile ions and, 
 a tunnel barrier layer having a thickness less than approximately 50 Angstroms; and 
   a selection device configured as a single Schottky diode including a single layer of an oxide semiconductor material in contact with a non-ohmic metal, the oxide semiconductor material including a graded doping profile having a doping concentration that is highest at an interface between the oxide semiconductor material and the non-ohmic metal, and the selection device and the ME are electrically in series with each other.