Method to automatically add power line in channel between macros

Abstract

A method includes detecting channels between macros in an integrated circuit. Each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value. The method also includes automatically adding at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel. The power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.

What is claimed is: 
     
         1 . A method comprising:
 detecting channels between macros in an integrated circuit, wherein each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value; and   automatically adding at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel, wherein the power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.   
     
     
         2 . The method of  claim 1 , wherein the device is coupled to at least one of a macro or signals propagating through the at least one channel. 
     
     
         3 . The method of  claim 1 , wherein the device is one of a decoupling capacitor to reduce power grid noise, a substrate well connector to prevent a latch-up violation, a buffer to reduce a propagation delay of signals in the at least one channel, or an inverter to reduce a propagation delay of signals in the at least one channel. 
     
     
         4 . The method of  claim 1 , further comprising detecting a power grid integrity within the channels prior to adding the at least one power line within the at least one channel. 
     
     
         5 . The method of  claim 1 , wherein the at least one channel is a vertical channel or a horizontal channel. 
     
     
         6 . The method of  claim 5 , wherein a first system power supply line disposed in a first metal layer of the integrated circuit connects with a first power line of the two power lines, and wherein a second system power supply line disposed in a second metal layer of the integrated circuit connects with a second power line of the two power lines. 
     
     
         7 . The method of  claim 6 , wherein the first power line and the second power line are disposed in a metal layer of the integrated circuit that is different than the first metal layer and the second metal layer. 
     
     
         8 . An automated circuit design tool comprising a non-transitory processor-readable medium having processor-executable instructions that are executable to cause a processor to:
 detect channels between macros in a circuit layout, wherein each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value; and   automatically add at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel, wherein the power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.   
     
     
         9 . The automated circuit design tool of  claim 8 , wherein the device is coupled to at least one of a macro or signals propagating through the at least one channel. 
     
     
         10 . The automated circuit design tool of  claim 8 , wherein the device is one of a decoupling capacitor to reduce power grid noise, a substrate well connector to prevent a latch-up violation, a buffer to reduce a propagation delay of signals in the at least one channel, or an inverter to reduce a propagation delay of signals in the at least one channel. 
     
     
         11 . The automated circuit design tool of  claim 8 , wherein the processor-executable instructions are further executable to cause the processor to detect a power grid integrity within the channels prior to adding the at least one power line within the at least one channel. 
     
     
         12 . The automated circuit design tool of  claim 8 , wherein a first system power supply line disposed in a first metal layer of the circuit layout connects with a first power line of the two power lines, and wherein a second system power supply line disposed in a second metal layer of the circuit layout connects with a second power line of the two power lines. 
     
     
         13 . The automated circuit design tool of  claim 12 , wherein the first power line and the second power line are disposed in a metal layer of the circuit layout that is different than the first metal layer and the second metal layer. 
     
     
         14 . An apparatus comprising:
 means for detecting channels between macros in an integrated circuit, wherein each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value; and   means for automatically adding at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel, wherein the power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.   
     
     
         15 . The apparatus of  claim 14 , wherein the device is coupled to at least one of a macro or signals propagating through the at least one channel. 
     
     
         16 . The apparatus of  claim 14 , wherein the device is one of a decoupling capacitor, a substrate well connector, a buffer, or an inverter. 
     
     
         17 . A non-transitory computer-readable medium embodying computer-readable data comprising a data file that represents a circuit designed using an automated circuit design tool, the circuit comprising:
 a first channel between at least two macro disposed in the circuit such that a shortest distance between the at least two macro satisfies a threshold value; and   a first power line, wherein an automated circuit design tool automatically added the first power line in the first channel in response to detecting a power integrity issue within the first channel, wherein the power integrity issue is satisfied by two power lines having opposite polarity being coupled to provide power to a device within the first channel.   
     
     
         18 . The non-transitory computer-readable medium of  claim 17 , wherein the device is coupled to at least one of a macro or signals propagating through the first channel. 
     
     
         19 . The non-transitory computer-readable medium of  claim 17 , wherein the device is one of a decoupling capacitor, a substrate well connector, a buffer, or an inverter. 
     
     
         20 . A circuit designed using an automated circuit design tool, the circuit comprising:
 a first channel between at least two macro disposed in the circuit such that a shortest distance between the at least two macro satisfies a threshold value; and   a first power line, wherein the automated circuit design tool automatically added the first power line in the first channel in response to detecting a power integrity issue within the first channel, wherein the power integrity issue is satisfied by two power lines having opposite polarity being coupled to provide power to a device within the first channel.   
     
     
         21 . The circuit of  claim 20 , wherein the device is coupled to at least one of macro or signals propagating through the first channel. 
     
     
         22 . The circuit of  claim 20 , wherein the device is one of a decoupling capacitor, a substrate well connector, a buffer, or an inverter.