Prefetching of next physically sequential cache line after cache line that includes loaded page table entry

Abstract

A microprocessor includes a translation lookaside buffer, a request to load a page table entry into the microprocessor generated in response to a miss of a virtual address in the translation lookaside buffer, and a prefetch unit. The prefetch unit receives a physical address of a first cache line that includes the requested page table entry and responsively generates a request to prefetch into the microprocessor a second cache line that is the next physically sequential cache line to the first cache line.

We claim: 
     
         1 : A microprocessor, comprising:
 a translation lookaside buffer;   a request to load a page table entry into the microprocessor generated in response to a miss of a virtual address in the translation lookaside buffer; and   a prefetch unit, configured to receive a physical address of a first cache line that includes the requested page table entry, wherein the prefetch unit is further configured to responsively generate a request to prefetch into the microprocessor a second cache line that is the next physically sequential cache line to the first cache line.   
     
     
         2 : The microprocessor of  claim 1 , wherein the second cache line is absent the page table entry implicated by the virtual address that missed in the translation lookaside buffer. 
     
     
         3 : The microprocessor of  claim 1 , further comprising:
 a tablewalk engine, configured to perform a tablewalk in response to the miss of the virtual address in the translation lookaside buffer, wherein the tablewalk does not access any of the page table entries in the prefetched second cache line.   
     
     
         4 . (canceled) 
     
     
         5 : The microprocessor of  claim 1 , wherein the request to load the page table entry, in response to which the prefetch unit prefetches the second cache line, is generated internally by the microprocessor in response to the miss of the virtual address in the translation lookaside buffer, rather than the load request being a load request of a program executed by the microprocessor. 
     
     
         6 : The microprocessor of  claim 1 , further comprising:
 a request to load a page directory entry into the microprocessor generated in response to the miss of the virtual address in the translation lookaside buffer;   wherein the prefetch unit is further configured to receive a physical address of a third cache line that includes the requested page directory entry, wherein the prefetch unit is further configured to responsively generate a second request to prefetch into the microprocessor a fourth cache line that is the next physically sequential cache line to the third cache line.   
     
     
         7 : A method for reducing tablewalk time by a microprocessor having a translation lookaside buffer, the method comprising:
 requesting to load a page table entry into the microprocessor, in response to a miss of a virtual address in the translation lookaside buffer;   receiving a physical address of a first cache line that includes the requested page table entry;   generating a request to prefetch into the microprocessor a second cache line that is the next physically sequential cache line to the first cache line, in response to said receiving the physical address of the first cache line that includes the requested page table entry.   
     
     
         8 : The method of  claim 7 , wherein the second cache line is absent the page table entry implicated by the virtual address that missed in the translation lookaside buffer. 
     
     
         9 : The method of  claim 7 , further comprising:
 performing a tablewalk in response to the miss of the virtual address in the translation lookaside buffer, wherein the tablewalk does not access any of the page table entries in the prefetched second cache line.   
     
     
         10 . (canceled) 
     
     
         11 : A microprocessor, comprising:
 a translation lookaside buffer;   a request to load a page table entry into the microprocessor generated in response to a miss of a virtual address in the translation lookaside buffer; and   a prefetch unit, configured to receive a physical address of a first cache line that includes the requested page table entry, wherein the prefetch unit is further configured to responsively generate a request to prefetch into the microprocessor a second cache line that is the previous physically sequential cache line to the first cache line.   
     
     
         12 : The microprocessor of  claim 11 , wherein the second cache line is absent the page table entry implicated by the virtual address that missed in the translation lookaside buffer. 
     
     
         13 : The microprocessor of  claim 11 , further comprising:
 a tablewalk engine, configured to perform a tablewalk in response to the miss of the virtual address in the translation lookaside buffer, wherein the tablewalk does not access any of the page table entries in the prefetched second cache line.   
     
     
         14 . (canceled) 
     
     
         15 : The microprocessor of  claim 11 , wherein the request to load the page table entry, in response to which the prefetch unit prefetches the second cache line, is generated internally by the microprocessor in response to the miss of the virtual address in the translation lookaside buffer, rather than the load request being a load request of a program executed by the microprocessor. 
     
     
         16 : The microprocessor of  claim 11 , further comprising:
 a request to load a page directory entry into the microprocessor generated in response to the miss of the virtual address in the translation lookaside buffer;   wherein the prefetch unit is further configured to receive a physical address of a third cache line that includes the requested page directory entry, wherein the prefetch unit is further configured to responsively generate a second request to prefetch into the microprocessor a fourth cache line that is the previous physically sequential cache line to the third cache line.   
     
     
         17 : A method for reducing tablewalk time by a microprocessor having a translation lookaside buffer, the method comprising:
 requesting to load a page table entry into the microprocessor, in response to a miss of a virtual address in the translation lookaside buffer;   receiving a physical address of a first cache line that includes the requested page table entry;   generating a request to prefetch into the microprocessor a second cache line that is the previous physically sequential cache line to the first cache line, in response to said receiving the physical address of the first cache line that includes the requested page table entry.   
     
     
         18 : The method of  claim 17 , wherein the second cache line is absent the page table entry implicated by the virtual address that missed in the translation lookaside buffer. 
     
     
         19 : The method of  claim 17 , further comprising:
 performing a tablewalk in response to the miss of the virtual address in the translation lookaside buffer, wherein the tablewalk does not access any of the page table entries in the prefetched second cache line.   
     
     
         20 . (canceled)