Die power structure

Abstract

A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles.

1 .- 9 . (canceled) 
     
     
         10 . The method of operating a die, comprising:
 distributing a first power signal having a first voltage across a first plurality of power tiles arranged in a first array and a first plurality of mesh segments;   distributing a second power signal having a second voltage across a second plurality of power tiles arranged in a second array and a second plurality of mesh segments,   wherein the first plurality of power tiles encloses the second plurality of mesh segments,   wherein the second plurality of power tiles encloses the first plurality of mesh segments, and   wherein the first array and the second array are offset on the die; and   propagating the first power signal to a first power rail operatively connected to the first plurality of power tiles and the first plurality of mesh segments by a first plurality of vias.   
     
     
         11 . The method of  claim 10 , further comprising:
 propagating the second power signal to a second power rail operatively connected to the second plurality of power tiles and the second plurality of mesh segments by a second plurality of vias.   
     
     
         12 . The method of  claim 11 , further comprising:
 injecting the first power signal into the die using a first bump above the second array and operatively connecting to the first plurality of power tiles using a zipper structure;   and injecting the second power signal into the die using a second bump above the first array and operatively connecting to the second plurality of power tiles using the zipper structure.   
     
     
         13 . The method of  claim 12 , further comprising:
 distributing the first power signal across a full-dense-mesh (FDM) operatively connecting the first bump to the zipper structure.   
     
     
         14 . The method of  claim 13 , wherein the FDM is in a M13 layer of the die, wherein the first plurality of power tiles and the second plurality of power tiles are in a M12 layer of the die, wherein the first plurality of mesh segments and the second plurality of mesh segments are in the M12 layer, and wherein the first power rail and the second power rail are in a M11 layer of the die below the M12 layer. 
     
     
         15 . The method of  claim 12 , further comprising:
 propagating a clock signal along the zipper structure.   
     
     
         16 . The method of  claim 12 , wherein the first bump and the second bump are separated by a bump pitch, wherein the first plurality of vias comprises a maximum inter-via distance, and wherein the maximum inter-via distance is less than the bump pitch. 
     
     
         17 . A method of manufacturing a die, comprising:
 generating a M12 layer of the die comprising a first plurality of power tiles arranged in a first array, a second plurality of power tiles arranged in a second array offset from the first array, and a first plurality of mesh segments enclosed by the second plurality of power tiles;   generating a M13 layer of the die comprising a first bump and a full-dense-mesh (FDM) operatively connected to the first plurality of mesh segments by a first plurality of vias; and   generating a M11 layer of the die comprising a first power rail operatively connected to the first plurality of power tiles and the first plurality of mesh segments by a second plurality of vias,   wherein the first plurality of power tiles, the first plurality of mesh segments, the first power rail, and the first bump are configured to have a first voltage, and   wherein the second plurality of tiles are configured to have a second voltage.   
     
     
         18 . The method of  claim 17 , wherein the M12 layer further comprises a second plurality of mesh segments enclosed by the first plurality of power tiles, wherein the M13 layer further comprises a second bump configured to have the second voltage, and wherein the M11 layer further comprises a second power rail operatively connected to the second plurality of mesh segments and the second plurality of power tiles by a third plurality of vias. 
     
     
         19 . The method of  claim 18 , wherein the first bump and the second bump are separated by a bump pitch, wherein the second plurality of vias comprises a maximum inter-via distance, and wherein the maximum inter-via distance is less than the bump pitch. 
     
     
         20 . The method of  claim 17 , wherein the FDM and the first plurality of power tiles are operatively connected by a zipper structure, and wherein the zipper structure is located between the first array and the second array.