US2014009194A1PendingUtilityA1

Phase locked loop circuit with selectable feedback paths

Assignee: LATTICE SEMICONDUCTOR CORPPriority: Apr 4, 2011Filed: Sep 9, 2013Published: Jan 9, 2014

Est. expiryApr 4, 2031(~4.7 yrs left)· nominal 20-yr term from priority

Inventors:Barry Britton Richard Booth Phillip Johnson Yang Xu David K. Li

H03L 7/095H03L 7/0802H03L 7/18H03L 2207/08H03L 7/14

PatentIndex Score

Cited by

References

Claims

Abstract

In one embodiment, a phase locked loop (PLL) circuit in a device includes selectable feedback paths and a multiplexer. An internal feedback path is adapted to pass a first input clock signal to the PLL circuit during a low power operation mode of the device and an external feedback path is adapted to pass a second input clock signal to the PLL circuit during a normal operation mode of the device. The multiplexer is provided for selecting between the internal and external feedback paths.

Claims

exact text as granted — not AI-modified

We claim: 
     
         1 . A phase locked loop (PLL) circuit comprising:
 an internal feedback path adapted to pass a first input clock signal to the PLL circuit during a low power operation mode of a device;   an external feedback path adapted to pass a second input clock signal to the PLL circuit during a normal operation mode of the device; and   a multiplexer for selecting between the internal feedback path and the external feedback path.

Join the waitlist — get patent alerts

Track US2014009194A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.