Compact High Speed Sense Amplifier for Non-Volatile Memory with Reduced layout Area and Power Consumption

Abstract

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

It is claimed: 
     
         1 . A sense amplifier for a memory circuit, comprising:
 a latch circuit;   an intermediate circuit, including a first node selectively connectable to one or more bit lines and a second node connectable to the latch circuit;   bit line selection circuitry connected to the first node, whereby the first node can selectively be connected to one or more bit lines;   a first switch connected to the latch circuit and the second node, whereby a value held in the latch circuit can be connected to the second node when on and isolate the latch circuit from the second node when off;   a second switch, whereby the latch circuit can be connected to a data bus;   a third switch whereby the second node can be connected to a node of the latch that holds the inverse of said value held in the latch circuit; and   a fourth switch connected between the second node and ground.   
     
     
         2 . The sense amplifier circuit of  claim 1 , wherein the intermediate circuit further includes an internal node connectable to the first node, the sense amplifier further comprising:
 a fifth switch whereby the internal node is selectively connectable to a voltage supply level.   
     
     
         3 . The sense amplifier circuit of  claim 2 , further comprising:
 a capacitor connected between the internal node and a third node.   
     
     
         4 . The sense amplifier circuit of  claim 3 , further comprising:
 a first transistor and a sixth switch connected in series between the third node and the second node, where the control gate of the first transistor is connected to the internal node.   
     
     
         5 . The sense amplifier circuit of  claim 1 , wherein outside of the latch circuit, the transistors of the sense amplifier are solely of the NMOS type. 
     
     
         6 . The sense amplifier circuit of  claim 1 , wherein the intermediate circuit further includes an internal node connectable to the first node, the sense amplifier, further comprising:
 a fifth switch whereby the first node is selectively connectable to the internal node.   
     
     
         7 . The sense amplifier circuit of  claim 1 , further comprising:
 a fifth switch whereby the first node is selectively connectable to the second node.   
     
     
         8 . The sense amplifier circuit of  claim 1 , further comprising:
 a fifth switch whereby the first node is selectively connectable to a voltage supply level independently of the value held in the latch circuit.   
     
     
         9 . A sense amplifier for a memory circuit, comprising:
 a latch circuit connected between a first voltage supply level and ground to hold a value latched therein;   an intermediate circuit, including a first node selectively connectable to one or more bit lines, a second node connectable to a node of the latch that holds the latched value, and an internal node connectable to the first node;   a first switch, whereby the node of the latch that holds the latched value can be connected to a data bus; and   a second switch whereby the internal node is selectively connectable to a second voltage supply level, where the first and second voltage supply levels are supplied from different on-chip supply levels.   
     
     
         10 . The sense amplifier of  claim 9 , wherein the first voltage supply level is a program inhibit level used for bit lines of the memory circuit. 
     
     
         11 . The sense amplifier of  claim 9 , wherein the second voltage supply level is a level used for pre-charging bit lines of the memory circuit for a sensing operation. 
     
     
         12 . The sense amplifier of  claim 9 , wherein the second voltage supply level has a higher voltage than the first voltage supply level. 
     
     
         13 . The sense amplifier of  claim 9 , wherein outside of the latch circuit, the transistors of the sense amplifier are solely of the NMOS type. 
     
     
         14 . The sense amplifier circuit of  claim 9 , further comprising:
 bit line selection circuitry connected to the first node, whereby the first node can selectively be connected to one or more bit lines; and   a first switch connected to the latch circuit and the second node, whereby a value held in the latch circuit can be connected to the second node when on and isolate the latch circuit from the second node when off.   
     
     
         15 . The sense amplifier circuit of  claim 14 , further comprising:
 a fourth switch whereby the second node can be connected to a node of the latch that holds the inverse of said value held in the latch circuit.   
     
     
         16 . The sense amplifier circuit of  claim 14 , further comprising:
 a capacitor connected between the internal node and a third node.   
     
     
         17 . The sense amplifier circuit of  claim 16 , further comprising:
 a first transistor and a fourth switch connected in series between the third node and the second node, where the control gate of the first transistor is connected to the internal node.   
     
     
         18 . The sense amplifier circuit of  claim 14 , further comprising:
 a fourth switch whereby the first node is selectively connectable to the internal node.   
     
     
         19 . The sense amplifier circuit of  claim 14 , further comprising:
 a fourth switch whereby the first node is selectively connectable to the second node.   
     
     
         20 . The sense amplifier circuit of  claim 14 , further comprising:
 a fourth switch whereby the first node is selectively connectable to the second voltage supply level independently of the value held in the latch circuit.   
     
     
         21 . A sense amplifier for a memory circuit, comprising:
 a latch circuit to hold a value latched therein;   an intermediate circuit, including a first node selectively connectable to one or more bit lines, a second node connectable to the latch circuit, and an internal node connectable to the first node;   bit line selection circuitry connected to the first node, whereby the first node can selectively be connected to one or more bit lines;   a first switch whereby the second node can be connected to a node of the latch that holds the latched value;   a second switch, whereby the node of the latch that holds the latched value can be connected to a data bus;   a third switch whereby the second node can be connected to a node of the latch that holds the inverse of the latched value; and   a first transistor and a fourth switch connected in series between a third node and the node of the latch that holds the latched value, where the control gate of the first transistor is connected to the internal node.   
     
     
         22 . The sense amplifier circuit of  claim 21 , further comprising:
 a capacitor connected between the internal node and a third node.   
     
     
         23 . The sense amplifier circuit of  claim 21 , wherein outside of the latch circuit, the transistors of the sense amplifier are solely of the NMOS type. 
     
     
         24 . The sense amplifier circuit of  claim 21 , further comprising:
 a fourth switch whereby the internal node is selectively connectable to a voltage supply level.   
     
     
         25 . The sense amplifier circuit of  claim 21 , further comprising:
 a fourth switch whereby the first node is selectively connectable to the internal node.   
     
     
         26 . The sense amplifier circuit of  claim 21 , further comprising:
 a fourth switch whereby the first node is selectively connectable to the second node.   
     
     
         27 . The sense amplifier circuit of  claim 21 , further comprising:
 a fourth switch whereby the first node is selectively connectable to a voltage supply level independently of the value held in the latch circuit.