Transistor with reduced charge carrier mobility and associated methods

Abstract

One or more embodiments relate to a method comprising: raising a potential of a first bit line and a second bit line; switching on a first n-channel access transistor coupled between the first bit line and a first node of a first inverter; switching on a second n-channel access transistor coupled between the second bit line and a second node of a second inverter; and reading a static random access memory (SRAM) cell including the first inverter and the second inverter by sensing a potential on the first bit line and a potential on the second bit line.

What is claimed is: 
     
         1 . A method comprising:
 raising a potential of a first bit line and a second bit line;   switching on a first n-channel access transistor coupled between the first bit line and a first node of a first inverter, the first inverter including a first p-channel load transistor coupled between a supply voltage and the first node and a first n-channel pull-down transistor coupled between the first node and a ground voltage, the first bit line being coupled to the supply voltage through the first p-channel load transistor and the first n-channel access transistor, a fin of the first n-channel access transistor having a lower charge carrier mobility than a fin of the first n-channel pull-down transistor;   switching on a second n-channel access transistor coupled between the second bit line and a second node of a second inverter, the second inverter including a second p-channel load transistor coupled between the supply voltage and the second node and a second n-channel pull-down transistor coupled between the second node and the ground voltage, the second bit line being coupled to the ground voltage through the second n-channel pull-down transistor and the second n-channel access transistor, a fin of the second n-channel access transistor having a lower charge carrier mobility than a fin of the second n-channel pull-down transistor; and   reading a static random access memory (SRAM) cell including the first inverter and the second inverter by sensing a potential on the first bit line and a potential on the second bit line.   
     
     
         2 . The method of  claim 1 , further comprising:
 setting the potential of the first bit line to a high programming voltage;   setting the potential of the second bit line to a low programming voltage;   switching on the first n-channel access transistor, a fin of the first p-channel load transistor having a lower charge carrier mobility than the fin of the first re-channel pull-down transistor; and   switching on the second n-channel access transistor to program the SRAM cell, a fin of the second p-channel load transistor having a lower charge carrier mobility than the fin of the second n-channel pull-down transistor.   
     
     
         3 . The method of  claim 1 , wherein switching on a first n-channel access transistor includes asserting a word line coupled to a gate of the first n-channel access transistor and to a gate of the second n-channel access transistor to switch on the first n-channel access transistor and the second n-channel access transistor. 
     
     
         4 . A method comprising:
 raising a potential of a first bit line and a second bit line;   switching on a first n-channel access transistor coupled between the first bit line and a first node of a first inverter;   switching on a second n-channel access transistor coupled between the second bit line and a second node of a second inverter; and   reading a static random access memory (SRAM) cell including the first inverter and the second inverter by sensing a potential on the first bit line and a potential on the second bit line.