Semiconductor device having hierarchical structured bit lines

Abstract

A semiconductor device includes first and second global bit lines; first, second, third and fourth sense node; a first sense switch coupled between the first sense node and the first global bit line; a second sense switch coupled between the second sense node and the second global bit line; a third sense switch coupled between the third sense node and the first global bit line; a fourth sense switch coupled between the fourth sense node and the second global bit line; a first sense amplifier including a first terminal coupled to the first sense node and a second terminal coupled to the second sense node; a second sense amplifier including a third terminal coupled to the third sense node and a fourth terminal coupled to the fourth sense node. The first, second, third and fourth terminals respectively have first, second, third and fourth parasitic capacitances substantially equal in capacitance value.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 first and second global bit lines;   first, second, third and fourth sense nodes;   a first sense switch coupled between the first sense node and the first global bit line;   a second sense switch coupled between the second sense node and the second global bit line;   a third sense switch coupled between the third sense node and the first global bit line;   a fourth sense switch coupled between the fourth sense node and the second global bit line;   a first sense amplifier including a first terminal coupled to the first sense node and a second terminal coupled to the second sense node;   a second sense amplifier including a third terminal coupled to the third sense node and a fourth terminal coupled to the fourth sense node;   a plurality of first local bit lines;   a plurality of first hierarchical switches each coupling an associated one of the first local bit lines to the first global bit line;   a plurality of second local bit lines; and   a plurality of second hierarchical switches each coupling an associated one of the second local bit lines to the second global bit line,   wherein first, second, third and fourth terminals respectively have first, second, third and fourth parasitic capacitances and the first, second, third and fourth parasitic capacitances are substantially equal in capacitance value to one another.   
     
     
         2 . The semiconductor device as claimed in  claim 1 , wherein each of the first hierarchical switches couples an associated one of the first local bit lines to the first global bit line without an intervention of any one of the first and third sense switches, and each of the second hierarchical switches couples an associated one of the second local bit lines to the second global bit line without an intervention of any one of the second and fourth sense switches. 
     
     
         3 . The semiconductor device as claimed in  claim 1 , further comprising:
 a plurality of first memory cells respectively allocated to the first local bit lines;   a plurality of second memory cells respectively allocated to the second local bit lines; and   a plurality of word lines each connected in common to an associated one of the first memory cells and an associated one of the second memory cells.   
     
     
         4 . The semiconductor device as claimed in  claim 1 , wherein the first and second global bit lines twist at least once between the first and second sense amplifiers. 
     
     
         5 . The semiconductor device as claimed in  claim 1 , wherein the first and second global bit lines twist at least twice between the first and second sense amplifiers. 
     
     
         6 . The semiconductor device as claimed in  claim 4 , wherein the first and second global bit lines twist an odd number of times between the first and second sense amplifiers. 
     
     
         7 . The semiconductor device as claimed in  claim 4 , wherein the first and second global bit lines twist an even number of times between the first and second sense amplifiers. 
     
     
         8 . The semiconductor device as claimed in  claim 1 , wherein each of the first hierarchical switches is disconnected from each of the first and third sense nodes and each of the second hierarchical switches is disconnected from each of the second and fourth sense nodes.