Semiconductor packages having increased input/output capacity and related methods

Abstract

A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a semiconductor chip;   a plurality of first leads;   a plurality of second leads, each of the second leads being disposed at least partially under the chip;   a plurality of bonding pads extending outside a periphery of the chip; and a plurality of connecting segments connecting each bonding pad to a respective one of the second leads;   wherein the connecting segments include an angular offset routing between the second leads and the bonding pads.   
     
     
         2 . The semiconductor package of  claim 1 , wherein upper surfaces of the first leads, the second leads, the bonding pads, and the connecting segments are coplanar. 
     
     
         3 . The semiconductor package of  claim 1 , further comprising a first metal plating layer configured on the upper surface of each of the first leads, the upper surface of each of the second leads, the upper surface of each of the bonding pads, and the upper surface of each of the connecting segments, wherein the upper surface of each of the first leads and the first metal plating layer above the upper surface of each of the first leads are enclosed within a package body, and the upper surface of each of the second leads and the first metal plating layer above the upper surface of each of the second leads are enclosed within a filling material. 
     
     
         4 . The semiconductor package of  claim 3 , further comprising a second metal plating layer configured on the lower surface of each of the first leads and the lower surface of each of the second leads, wherein the bonding pads and the connecting segments are not covered by the second metal plating layer. 
     
     
         5 . The semiconductor package of  claim 1 , further comprising a filling material occupying spaces between the chip and the second leads. 
     
     
         6 . The semiconductor package of  claim 5 , further comprising a package body, and wherein a material of the filling material and a material of the package body are the same. 
     
     
         7 . A semiconductor package, comprising:
 a semiconductor chip;   a plurality of first leads;   a plurality of second leads, each of the second leads being disposed at least partially under the chip;   a plurality of bonding pads extending outside a periphery of the chip; and   a plurality of connecting segments connecting each bonding pad to a respective one of the second leads;   wherein the connecting segments include an angular offset routing between the second leads and the bonding pads.   
     
     
         8 . The semiconductor package of  claim 7 , wherein an undersurface of the semiconductor chip is elevated above the upper surfaces of the first leads and the bonding pads. 
     
     
         9 . The semiconductor package of  claim 7 , wherein the first leads have an upper sloped portion and a lower sloped portion meeting at a peak. 
     
     
         10 . The semiconductor package of  claim 9 , further comprising a package body that at least partially surrounds the peaks of the first leads to provide a mechanical hold on the first leads. 
     
     
         11 . The semiconductor package of  claim 7 , further comprising a plurality of connecting segments connecting each bonding pad to a respective one of the second leads, wherein upper surfaces of the connecting segments are coplanar with the upper surfaces of the first leads, the second leads, and the bonding pads. 
     
     
         12 . The semiconductor package of  claim 7 , wherein upper surfaces of the second leads do not include a metal plating layer. 
     
     
         13 . The semiconductor package of  claim 7 , further comprising a filling material occupying spaces between the chip and the second leads. 
     
     
         14 . The semiconductor package of  claim 13 , further comprising a package body, and wherein a material of the filling material and a material of the package body are the different. 
     
     
         15 . A semiconductor package, comprising:
 a semiconductor chip;   a plurality of leads, a portion of the leads being disposed at least partially under the chip;   a plurality of bonding pads extending outside a periphery of the chip;   a plurality of connecting segments connecting each bonding pad to a respective one of the leads; and   a filling material occupying spaces between the chip and the portion of the leads that are disposed at least partially under the chip;   wherein the connecting segments include an angular offset routing between the leads and the bonding pads.   
     
     
         16 . The semiconductor package of  claim 15 , further comprising a package body, and wherein a material of the filling material and a material of the package body are different. 
     
     
         17 . The semiconductor package of  claim 15 , wherein upper surfaces of the leads, the bonding pads and the connecting segments are coplanar. 
     
     
         18 . A semiconductor packaging process, comprising:
 forming a patterned first metal plating layer on a top surface of a conductive substrate, wherein the first metal plating layer comprises a plurality of first lead metal patterns located outside of a chip bonding region of the substrate, a plurality of bonding pad metal patterns located outside of the chip bonding region, a plurality of second lead metal patterns located within the chip bonding region, and a plurality of connecting segment metal patterns extending between the second lead metal patterns and the bonding pad metal patterns;   performing a half etching process on the top surface of the conductive substrate to form recessed areas in the top surface, including recessed areas in the chip bonding region;   bonding a semiconductor chip in the chip bonding region of the conductive substrate;   wire bonding the semiconductor chip to the bonding pad metal patterns and to the first lead metal patterns through a plurality of bonding wires; and   etching an undersurface of the conductive substrate to form a plurality of first leads located outside of the chip bonding region, a plurality of bonding pads located outside of the chip bonding region, a plurality of second leads located within the chip bonding region, and a plurality of connecting segments extending between the second leads and the bonding pads, wherein the connecting segments include an angular offset routing between the second leads and the bonding pads.   
     
     
         19 . The semiconductor packaging process of  claim 18 , further comprising forming a patterned second metal plating layer on an undersurface of the conductive substrate. 
     
     
         20 . The semiconductor packaging process of  claim 18 , further comprising inserting a filling material into the recessed areas in the chip bonding region.