Self-aligned si rich nitride charge trap layer isolation for charge trap flash memory

Abstract

A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance. U-shaped trap layer edges allow for increased packing density and integration while maintaining isolation between trap layers.

1 - 11 . (canceled) 
     
     
         12 . A memory device, comprising:
 a semiconductor substrate;   a plurality of active regions;   a plurality of trenches separating the active regions;   a plurality of self-aligned charge trapping structures disposed over the plurality of active regions, wherein the charge trapping structures are substantially U-shaped.   
     
     
         13 . The memory device of  claim 12 , wherein the self-aligned charge trapping structures are formed through a sacrificial top oxide, organic bottom antireflective coating planarization, organic bottom antireflective coating etch back, sacrificial top oxide etch, nitride etch, organic bottom antireflective coating removal and cleaning, sacrificial top oxide removal and cleaning, top oxide formation and polysilicon deposit, wherein the sacrificial top oxide and nitride are not etched over the active regions. 
     
     
         14 . The memory device of  claim 12 , wherein the active regions have had corners which underwent a rounding process before the plurality of charge trapping structures were formed. 
     
     
         15 . The memory device of  claim 14 , wherein the corners are rounded through a liner oxide process. 
     
     
         16 . The memory device of  claim 12 , wherein the charge trapping structures comprise an oxide-nitride-oxide structure. 
     
     
         17 . The memory device of  claim 16 , wherein the nitride of the oxide-nitride-oxide structure is comprised of silicon rich nitride. 
     
     
         18 . The memory device of  claim 16 , wherein the nitride of the oxide-nitride-oxide structure is comprised of nitride on top of silicon rich nitride. 
     
     
         19 . The memory device of  claim 16 , wherein the nitride of the oxide-nitride-oxide structure is comprised of a plurality of nitride layers having different amounts of silicon. 
     
     
         20 . The memory device of  claim 13 , wherein the organic bottom antireflective coating is replaced with other materials suitable for use in planarization. 
     
     
         21 . The memory device of  claim 13 , wherein the sacrificial top oxide layer is between 20-100 angstroms (Å) thick. 
     
     
         22 . A system comprising:
 a processor;   a bus coupled to the processor;   a non-volatile memory coupled to the bus, wherein the non-volatile memory comprises:
 a semiconductor substrate; 
 a plurality of active regions; 
 a plurality of trenches separating the active regions; 
 a plurality of self-aligned charge trapping structures disposed over the plurality of active regions, wherein the charge trapping structures are substantially U-shaped. 
   
     
     
         23 . The system of  claim 22 , wherein the self-aligned charge trapping structures are formed through a sacrificial top oxide, organic bottom antireflective coating planarization, organic bottom antireflective coating etch back, sacrificial top oxide etch, nitride etch, organic bottom antireflective coating removal and cleaning, sacrificial top oxide removal and cleaning, top oxide formation and polysilicon deposit, wherein the sacrificial top oxide and nitride are not etched over the active regions. 
     
     
         24 . The system of  claim 22 , wherein the active regions have rounded corners. 
     
     
         25 . The system of  claim 22 , wherein the processor, bus, and non-volatile memory comprise an image capture device. 
     
     
         26 . The system of  claim 22 , wherein the processor, bus, and non-volatile memory comprise a communications device. 
     
     
         27 . The system of  claim 22 , wherein the processor, bus, and non-volatile memory comprise a computing device.