Error detection and offset cancellation during multi-wire communication

Abstract

Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.

What is claimed is: 
     
         1 . An integrated circuit (IC) device comprising:
 transmit circuitry to transmit N symbols encoded as M symbols over M links to a second IC device;   a receiver to receive error information from the second IC device, the error information associated with the transmitted symbols; and   control logic operative to carry out a remedial operation based on the received error information.   
     
     
         2 . The integrated circuit device according to  claim 1 , wherein:
 the encoding results in the symbols being transmitted as a balanced codeword; and   the error information results from detection of an imbalance in the codeword at the second IC device.   
     
     
         3 . The integrated circuit device according to  claim 1 , wherein the remedial operation involves re-transmitting at least a portion of the M symbols. 
     
     
         4 . The integrated circuit device according to  claim 1 , wherein the remedial operation involves storing information regarding one or more links associated with the error information. 
     
     
         5 . The integrated circuit device according to  claim 1 , wherein the remedial operation involves adjusting a transmit parameter associated with the transmit circuitry. 
     
     
         6 . The integrated circuit according to  claim 5 , wherein the transmit parameter is selected from the group consisting of amplitude, gain, and timing. 
     
     
         7 . The integrated circuit according to  claim 1 , wherein the control logic accumulates an error count and calculates a performance parameter. 
     
     
         8 . The integrated circuit according to  claim 7 , wherein the performance parameter is selected from the group consisting of BER and SNR. 
     
     
         9 . The integrated circuit according to  claim 1 , wherein the encoded M symbols are transmitted in accordance with a modulation scheme, and wherein the control logic is operative to adjust the modulation scheme based on the error information. 
     
     
         10 . The integrated circuit device according to  claim 1  embodied as a memory controller. 
     
     
         11 . A system comprising:
 a first integrated circuit (IC) device having transmit circuitry to transmit N symbols encoded as M symbols;   a second IC device;   a set of M links to transfer the M symbols from the first IC device to the second IC device; and   wherein the first IC further includes
 a receiver to receive error information from the second IC, the error information associated with the transmitted symbols; and 
 control logic operative to carry out a remedial operation based on the received error information. 
   
     
     
         12 . The system of  claim 11  wherein:
 the encoding results in the symbols being transmitted as a balanced codeword; and 
 the error information results from detection of an imbalance in the codeword at the second IC device. 
 
     
     
         13 . The system of  claim 11  wherein the remedial operation involves re-transmitting at least a portion of the M symbols. 
     
     
         14 . The system of  claim 11  wherein the remedial operation involves storing information regarding one or more links associated with the error information. 
     
     
         15 . The system of  claim 11  wherein the remedial operation involves adjusting a transmit parameter associated with the transmit circuitry. 
     
     
         16 . The system of  claim 15  wherein the transmit parameter is selected from the group consisting of amplitude, gain, and timing. 
     
     
         17 . The system of  claim 11  wherein the control logic accumulates an error count and calculates a performance parameter. 
     
     
         18 . The system of  claim 17 , wherein the performance parameter is selected from the group consisting of BER and SNR. 
     
     
         19 . The system of  claim 11 , wherein the first IC comprises a memory controller, and the second IC comprises a memory device. 
     
     
         20 . An integrated circuit comprising:
 means for transmitting N symbols encoded as M symbols over M links to a second IC device;   means for receiving error information from the second IC device, the error information associated with the transmitted symbols; and   means for carrying out a remedial operation based on the received error information.