US2013342184A1PendingUtilityA1
Monolithic Group III-V Power Converter
Est. expiryDec 11, 2026(~0.4 yrs left)· nominal 20-yr term from priority
Inventors:Michael A. Briere
H10D 84/08H10D 62/8503H10D 89/105H10D 84/01H10D 30/4755G11C 5/14G11C 7/00H02M 3/1588H02M 3/155G05F 1/10Y02B70/10
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Claims
Abstract
A power arrangement that includes a monolithically integrated III-nitride power stage having III-nitride power switches and III-nitride driver switches.
Claims
exact text as granted — not AI-modified1 - 42 . (canceled)
43 - 55 . (canceled)
56 : A power management arrangement comprising:
a driver stage including a first III-Nitride transistor and a second III-Nitride transistor; said driver stage configured to drive a III-Nitride power switch; said III-Nitride power switch configured to power a load stage; said load stage including a control circuitry configured to provide control signals to said driver stage.
57 : The power management arrangement of claim 56 wherein said driver stage including said first III-Nitride transistor and said second III-Nitride transistor, and said III-Nitride power switch are integrated in a single substrate.
58 : The power management arrangement of claim 56 wherein said second III-Nitride transistor, and said III-Nitride power switch comprise high electron mobility transistors (HEMTs).
59 : The power management arrangement of claim 56 wherein said first III-Nitride transistor and said second III-Nitride transistor are enhancement mode devices, and said III-Nitride power switch is a depletion mode device.
60 : The power management arrangement of claim 56 wherein one of said first III-Nitride transistor and said second III-Nitride transistor is an enhancement mode device.
61 : The power management arrangement of claim 56 wherein one of said first III-Nitride transistor and said second III-Nitride transistor is a depletion mode device.
62 : The power management arrangement of claim 56 further comprising:
another III-Nitride power switch;
said driver stage including a third III-Nitride transistor and a fourth III-Nitride transistor for driving said another III-Nitride power switch.
63 : The power management arrangement of claim 62 wherein one of said III-Nitride power switch and said another III-Nitride power switch is an enhancement mode device.
64 : The power management arrangement of claim 62 wherein one of said III-Nitride power switch and said another III-Nitride power switch is a depletion mode device.
65 : A power management arrangement comprising:
a driver stage including an enhancement mode III-Nitride transistor and a depletion mode III-Nitride transistor; said driver stage configured to drive a III-Nitride power switch; said III-Nitride power switch configured to power a load stage; said load stage including a control circuitry configured to provide control signals to said driver stage.
66 : The power management arrangement of claim 65 wherein said driver stage including said enhancement mode III-Nitride transistor and said depletion mode III-Nitride transistor, and said III-Nitride power switch are integrated in a single substrate.
67 : The power management arrangement of claim 65 wherein said enhancement mode III-Nitride transistor, said depletion mode III-Nitride transistor, and said III-Nitride power switch comprise high electron mobility transistors (HEMTs).
68 : The power management arrangement of claim 65 further comprising:
another III-Nitride power switch;
said driver stage including another enhancement mode III-Nitride transistor and another depletion mode III-Nitride transistor for driving said another III-Nitride power switch.
69 : The power management arrangement of claim 68 wherein one of said III-Nitride power switch and said another III-Nitride power switch is an enhancement mode device.
70 : The power management arrangement of claim 68 wherein one of said III-Nitride power switch and said another III-Nitride power switch is a depletion mode device.
71 : A power management device comprising:
a monolithic semiconductor die integrated on a silicon substrate; said monolithic semiconductor die having a first III-nitride power semiconductor device and a second III-nitride power semiconductor device coupled to said first III-nitride power semiconductor device in a half-bridge configuration; said half-bridge configuration including a first driver half-bridge arrangement and a second driver half-bridge arrangement.
72 : The power management device of claim 71 , wherein said first driver half-bridge arrangement comprises an enhancement mode III-nitride switch.
73 : The power management device of claim 71 , wherein said second driver half-bridge arrangement comprises an enhancement mode III-nitride switch.
74 : The power management device of claim 71 , wherein said first driver half-bridge arrangement comprises a depletion mode III-nitride switch.
75 : The power management device of claim 71 , wherein said second driver half-bridge arrangement comprises a depletion mode III-nitride switch.Join the waitlist — get patent alerts
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