Semiconductor device

Abstract

A technique for improving the characteristics of a semiconductor device (UMOSFET) is provided. In the UMOSFET in order to grow an epitaxial growth film on a trench side wall with an even film thickness, a channel is arranged in an optimum direction as a growth surface. For example, a trench is formed on an SiC substrate having a {0001} surface 4° off in a <11-20> direction as a main surface so that a channel surface becomes a {1-100} surface. With this configuration, an epitaxial growth with the even thickness can be conducted on the side wall from which the {1-100} surface of the trench is exposed. As a result, the unevenness of a channel resistance, and the insulation failure of a gate insulating film do not occur, and the yield is improved.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a trench having two surfaces parallel to an off angle direction, and two or more other surfaces on a first surface side of a substrate; and   an epitaxial growth layer on a trench inner wall.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein an area per one of the two surfaces parallel to the off angle direction of the trench is larger than any area of the other surfaces.   
     
     
         3 . A semiconductor device, comprising:
 a channel region including two surfaces parallel to an off angle direction of a trench;   a first source region of a first conduction type which is arranged above a first surface side of a substrate;   a first semiconductor region of a second conduction type which is arranged below the first source region, and has a channel region;   a second semiconductor region of the first conduction type which contacts with the first semiconductor region;   a gate electrode arranged above the channel region through a gate insulating film; and   a buried semiconductor region of the second conduction type which is arranged in the first semiconductor region.   
     
     
         4 . The semiconductor device according to  claim 3 ,
 wherein the first source region is connected to a first line.   
     
     
         5 . The semiconductor device according to  claim 3 ,
 wherein the second semiconductor region is connected with a drain electrode arranged on a second surface side of the substrate.   
     
     
         6 . The semiconductor device according to  claim 3 ,
 wherein the gate electrode is out of contact with the gate insulating film in surfaces other than the two surfaces parallel to the off angle direction of the trench.   
     
     
         7 . A semiconductor device, comprising:
 a channel region including two surfaces parallel to an off angle direction of a trench;   a first source region of a first conduction type which is arranged above a first surface side of a substrate;   a first semiconductor region of a second conduction type which is arranged below the first source region, and has a channel region;   a second semiconductor region of the second conduction type which contacts with the first semiconductor region;   a gate electrode arranged above the channel region through a gate insulating film; and   a buried semiconductor region of the second conduction type which is arranged in the first semiconductor region.   
     
     
         8 . The semiconductor device according to  claim 7 ,
 wherein the first source region is connected to a first line.   
     
     
         9 . The semiconductor device according to  claim 7 ,
 wherein the second semiconductor region is connected with a drain electrode arranged on a second surface side of the substrate.   
     
     
         10 . The semiconductor device according to  claim 7 ,
 wherein the gate electrode is out of contact with the gate insulating film in surfaces other than the two surfaces parallel to the off angle direction of the trench.