US2013341596A1PendingUtilityA1

Nanowire fet and finfet

Individually held — no corporate assignee on recordPriority: Jun 21, 2012Filed: Jul 13, 2012Published: Dec 26, 2013
Est. expiryJun 21, 2032(~5.9 yrs left)· nominal 20-yr term from priority
H10D 86/215H10D 62/121H10D 30/6757H10D 30/6735H10D 30/43H10D 86/011B82Y 10/00
47
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Claims

Abstract

A complimentary metal oxide semiconductor (CMOS) device includes a wafer having a buried oxide (BOX) layer having a first region with a first thickness and a second region with a second thickness, the first thickness is less than the second thickness, a nanowire field effect transistor (FET) arranged on the BOX layer in the first region, the nanowire FET, and a finFET arranged on the BOX layer in the second region.

Claims

exact text as granted — not AI-modified
1 . A complementary metal oxide semiconductor (CMOS) device, comprising:
 a wafer having a buried oxide (BOX) layer;   a nanowire field effect transistor (FET) arranged on the BOX layer, the nanowire FET comprising:
 nanowires and pads attached to the opposing ends of the nanowires, wherein the nanowires are suspended over the BOX layer by the pads arranged on the BOX layer; and 
 a first gate stack that surrounds at least a portion of each of the nanowires, wherein the portions of the nanowires surrounded by the first gate stack define a channel region of the nanowire FET; and 
 a finFET arranged on the BOX layer, the FinFET comprising: 
 a plurality of fins; and 
 a second gate stack covering at least a portion of each of the fins, wherein the portion of the fins covered by the second gate stack defines a channel region of the FinFET; and 
 an epitaxial material simultaneously grown on exposed portions of the nanowires, the pads and the fins, wherein the epitaxial material simultaneously grown on the exposed portions of the nanowires and the pads define source and drain regions of the nanowire FET and wherein the epitaxial material simultaneously grown on the exposed portions of the fins defines source and drain regions of the finFET. 
   
     
     
         2 . The device of  claim 1 , further comprising spacers arranged at opposing sides of the first gate stack and on opposite sides of the second gate stack. 
     
     
         3 - 5 . (canceled) 
     
     
         6 . The device of  claim 1 , further comprising a contact material arranged on the epitaxial material. 
     
     
         7 . The device of  claim 1 , further comprising a contact material arranged on the epitaxial material. 
     
     
         8 . The device of  claim 1 , further comprising a contact material arranged on the epitaxial material. 
     
     
         9 . The device of  claim 1 , wherein the first gate stack comprises:
 a conformal gate dielectric film arranged around the nanowires;   conformal metal gate film over the conformal gate dielectric film; and   polysilicon over the conformal metal gate film.   
     
     
         10 . The device of  claim 9 , wherein the conformal gate dielectric film is selected from a group consisting of: silicon dioxide, silicon oxynitride and hafnium oxide. 
     
     
         11 . The device of  claim 9 , wherein the conformal metal gate film is selected from a group consisting of: tantalum nitride and titanium nitride. 
     
     
         12 . The device of  claim 1 , wherein the second gate stack comprises:
 a gate dielectric arranged over the fins; and   a polysilicon over the gate dielectric.   
     
     
         13 . The device of  claim 12 , wherein the conformal gate dielectric film is selected from a group consisting of: silicon dioxide, silicon oxynitride and hafnium oxide. 
     
     
         14 - 20 . (canceled) 
     
     
         21 . The device of  claim 1 , wherein the epitaxial material simultaneously grown on the exposed portions of the fins merges the fins together.

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