Semiconductor process

Abstract

A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.

What is claimed is: 
     
         1 . A semiconductor process, comprising:
 forming a polysilicon layer on a substrate;   cryo-implanting the polysilicon layer with at least two of a plurality of species comprising a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between −40° C. and −120° C.; and   performing an asymmetric dual-side heating treatment to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.   
     
     
         2 . The semiconductor process according to  claim 1 , wherein the power for the backside heating is greater than the power for the front-side heating. 
     
     
         3 . The semiconductor process according to  claim 2 , wherein a power ratio of the front-side heating to the backside heating ranges between 0.1:1 and 0.5:1. 
     
     
         4 . The semiconductor process according to  claim 3 , wherein the power ratio of the front-side heating to the backside heating is 0.2:1. 
     
     
         5 . A semiconductor process, comprising:
 forming an isolation structure in a substrate;   forming a polysilicon layer on the isolation structure; and   cryo-implanting the polysilicon layer with at least two of a plurality of species comprising a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between −40° C. and −120° C.   
     
     
         6 . The semiconductor process according to  claim 5 , wherein the step of cryo-implanting the polysilicon layer is performed with liquid nitrogen or at a temperature of −100° C. 
     
     
         7 . The semiconductor process according to  claim 5 , wherein the third species comprises a boron species. 
     
     
         8 . The semiconductor process according to  claim 5 , wherein the third species is cryo-implanted into the polysilicon layer after cryo-implanting the first species and the second species. 
     
     
         9 . The semiconductor process according to  claim 5 , after the polysilicon layer is cryo-implanted with the first species, the second species and the third species, further comprising: performing an asymmetric dual-side heating treatment to the substrate, wherein a power for a front-side heating is different from a power for a backside heating. 
     
     
         10 . The semiconductor process according to  claim 9 , wherein the power for the backside heating is greater than the power for the front-side heating. 
     
     
         11 . The semiconductor process according to  claim 10 , wherein a power ratio of the front-side heating to the backside heating ranges between 0.1:1 and 0.5:1. 
     
     
         12 . The semiconductor process according to  claim 11 , wherein the power ratio of the front-side heating to the backside heating is 0.2:1. 
     
     
         13 . The semiconductor process according to  claim 9 , wherein the asymmetric dual-side heating treatment comprises a spike annealing process. 
     
     
         14 . A semiconductor process, comprising:
 forming an isolation structure in a substrate;   forming a polysilicon stack on the isolation structure;   forming a gate structure on the substrate;   cryo-implanting the polysilicon stack with at least two of a plurality of species comprising a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between −40° C. and −120° C.;   forming doped regions in the substrate adjacent to respective sides of the gate structure; and   performing an asymmetric dual-side heating treatment to the substrate for annealing the polysilicon stack and for activating the doped regions, wherein a power for a front-side heating is different from a power for a backside heating.   
     
     
         15 . The semiconductor process according to  claim 14 , wherein the step of cryo-implanting the polysilicon stack is performed with liquid nitrogen or at a temperature of −100° C. 
     
     
         16 . The semiconductor process according to  claim 14 , wherein the third species comprises a boron species. 
     
     
         17 . The semiconductor process according to  claim 14 , wherein the third species is cryo-implanted into the polysilicon stack after cryo-implanting the first species and the second species. 
     
     
         18 . The semiconductor process according to  claim 14 , wherein the power for the backside heating is greater than the power for the front-side heating. 
     
     
         19 . The semiconductor process according to  claim 18 , wherein a power ratio of the front-side heating to the backside heating ranges between 0.1:1 and 0.5:1. 
     
     
         20 . The semiconductor process according to  claim 19 , wherein the power ratio of the front-side heating to the backside heating is 0.2:1. 
     
     
         21 . The semiconductor process according to  claim 14 , wherein the asymmetric dual-side heating treatment comprises a spike annealing process. 
     
     
         22 . The semiconductor process according to  claim 14 , further comprising: performing a laser annealing process to the substrate after performing the asymmetric dual-side heating treatment. 
     
     
         23 . A semiconductor process, comprising:
 forming an isolation structure in a substrate;   forming a polysilicon stack on the isolation structure;   forming a gate structure on the substrate, wherein the gate structure and the polysilicon stack are formed simultaneously;   cryo-implanting the polysilicon stack with at least two of a plurality of species comprising a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between −40° C. and −120° C.;   forming doped regions in the substrate adjacent to respective sides of the gate structure; and   performing an asymmetric dual-side heating treatment to the substrate for annealing the polysilicon stack and for activating the doped regions, wherein a power for a front-side heating is different from a power for a backside heating.   
     
     
         24 . The semiconductor process according to  claim 23 , wherein the third species is cryo-implanted into the polysilicon stack after cryo-implanting the first species and the second species. 
     
     
         25 . The semiconductor process according to  claim 23 , wherein the power for the backside heating is greater than the power for the front-side heating. 
     
     
         26 . The semiconductor process according to  claim 25 , wherein a power ratio of the front-side heating to the backside heating ranges between 0.1:1 and 0.5:1. 
     
     
         27 . The semiconductor process according to  claim 23 , wherein the asymmetric dual-side heating treatment comprises a spike annealing process. 
     
     
         28 . The semiconductor process according to  claim 23 , further comprising: performing a laser annealing process to the substrate after performing the asymmetric dual-side heating treatment.