I-q mismatch calibration and method

Abstract

Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed.

1 . An apparatus comprising:
 an in-phase (I) signal path and a quadrature (Q) signal path; and   means for applying an offset between a bias for an element of the I signal path and a bias for an element of the Q signal path.   
     
     
         2 . The apparatus of  claim 1 , further comprising:
 means for determining an optimal offset to be applied.   
     
     
         3 . The apparatus of  claim 2 , further comprising means for generating a bias voltage for an element of the I signal path and a bias voltage for an element of the Q signal path. 
     
     
         4 . A computer program product for specifying an offset to be applied between an element of an I signal path and an element of a corresponding Q signal path in a communications apparatus, the product comprising:
 computer-readable medium comprising:   code for causing a computer to measure I and Q input signals coupled to outputs of the I and Q signal paths, respectively; and   code for causing a computer to adjust the applied offset based on the measured I and Q input signals.   
     
     
         5 . The computer program product of  claim 4 , the code for causing a computer to adjust the applied offset based on the measured I and Q input signals comprising:
 code for causing a computer to adjust the applied offset based on a residual sideband measured from the I and Q input signals.   
     
     
         6 . The computer program product of  claim 5 , the communications apparatus comprising a transmitter, a duplexer, and a receiver, the product further comprising:
 code for causing a computer to transmit a controlled input signal to the input of the receiver via the duplexer using the transmitter.   
     
     
         7 . The computer program product of  claim 6 , further comprising code for applying a plurality of candidate offsets between a bias for an element of the I signal path and a bias for an element of the Q signal path; and code for measuring I and Q input signals coupled to the outputs of the I and Q mixers for each of the plurality of candidate offsets applied. 
     
     
         8 . An apparatus for converting two digitally specified voltages into two analog voltages, the two digitally specified voltages comprising a first digital signal and a second digital signal, the two analog voltages being generated at a first output node and a second output node, the conversion module comprising:
 a voltage digital-to-analog converter for converting the first digital signal to a first analog voltage;   a unidirectional current digital-to-analog converter for converting the second digital signal to a second analog current at a current node;   a first set of switches coupling, when the switches are turned on, the first analog voltage to the current node via the first output node and a resistance; and   a second set of switches coupling, when the switches are turned on, the first analog voltage to the current node via the second output node and a resistance.   
     
     
         9 . The apparatus of  claim 8 , further comprising:
 a first buffer coupling the first analog voltage to the first output node when the first switches are turned on; and   a second buffer coupling the first analog voltage to the second output node when the second switches are turned on.   
     
     
         10 . The apparatus of  claim 8 , the resistance being adjustable in response to a control signal. 
     
     
         11 . The apparatus of  claim 8 , the voltage digital-to-analog converter comprising a resistor chain. 
     
     
         12 . A non-transitory processor-readable medium having stored thereon processor executable instructions configured to cause a processor within a communication apparatus to perform operations for reducing mismatch between in-phase (I) and quadrature (Q) signal paths in a communications apparatus comprising:
 applying an offset between a bias for an element of the I signal path and a bias for an element of the Q signal path;   applying at least one I local oscillator signal to the I signal path; and   applying at least one Q local oscillator signal to the Q signal path.   
     
     
         13 . The non-transitory processor-readable medium of  claim 12 , wherein the stored processor-executable instructions are configured to be executed by a processor of a communication apparatus that comprises a receiver. 
     
     
         14 . The non-transitory processor-readable medium of  claim 12 , wherein the stored processor-executable instructions are configured to be executed by a processor of a communication apparatus that comprises a transmitter, the transmitter comprising the I and Q signal paths. 
     
     
         15 . The non-transitory processor-readable medium of  claim 12 , wherein the stored processor-executable instructions are configured to be executed by a processor of a communication apparatus in which the I and Q signal paths comprise corresponding I and Q mixers, and wherein the stored processor-executable instructions are configured to cause a processor within a communication apparatus to perform operations such that applying an offset further comprises applying an offset between a transistor in the I mixer and a corresponding transistor in the Q mixer. 
     
     
         16 . The non-transitory processor-readable medium of  claim 15 , wherein the stored processor-executable instructions are configured to cause a processor within a communication apparatus to perform operations such that applying an offset further comprises applying an offset between the gate of the transistor in the I mixer and the gate of the corresponding transistor in the Q mixer. 
     
     
         17 . The non-transitory processor-readable medium of  claim 15 , wherein the stored processor-executable instructions are configured to cause a processor within a communication apparatus to perform operations further comprising:
 applying a bias offset between a first transistor in the I mixer and a second transistor in the I mixer, the first and second transistors forming a differential pair.   
     
     
         18 . The non-transitory processor-readable medium of  claim 15 , wherein the stored processor-executable instructions are configured to cause a processor within a communication apparatus to perform operations such that applying an offset further comprises applying an offset between the bulk of the transistor in the I mixer and the bulk of the corresponding transistor in the Q mixer. 
     
     
         19 . The non-transitory processor-readable medium of  claim 16 , wherein the stored processor-executable instructions are configured to cause a processor within a communication apparatus to perform operations such that applying an offset further comprises applying an offset between the bulk of the transistor in the I mixer and the bulk of the corresponding transistor in the Q mixer. 
     
     
         20 . The non-transitory processor-readable medium of  claim 15 , wherein the stored processor-executable instructions are configured to be executed by a processor of a communication apparatus in which each mixer is an active mixer and each active mixer comprises at least one biasing transistor,
 wherein the stored processor-executable instructions are configured to cause a processor in a communication apparatus to perform operations such that applying an offset further comprises applying an offset between the bias current associated with the at least one biasing transistor in the I mixer and the at least one biasing transistor in the Q mixer.   
     
     
         21 . The non-transitory processor-readable medium of  claim 15 , wherein the stored processor-executable instructions are configured to be executed by a processor of a communication apparatus in which the I and Q signal paths comprise corresponding I and Q mixers and corresponding I and Q transimpedance amplifiers (TIA's) coupled to the outputs of the I and Q mixers, respectively, and
 wherein the stored processor-executable instructions are configured to cause a processor in a communication apparatus to perform operations such that applying an offset further comprises applying an offset between a bias voltage of the I TIA and a corresponding bias voltage of the Q TIA.   
     
     
         22 . The non-transitory processor-readable medium of  claim 21 , wherein the stored processor-executable instructions are configured to be executed by a processor of a communication apparatus in which the bias voltage of the I TIA comprises a common-mode output voltage of the I TIA, and the bias voltage of the Q TIA comprises a common-mode output voltage of the Q TIA. 
     
     
         23 . The non-transitory processor-readable medium of  claim 12 , wherein the stored processor-executable instructions are configured to be executed by a processor of a communication apparatus in which the I and Q signal paths comprise corresponding I and Q mixers and corresponding I and Q Gm amplifiers coupled to the inputs of the I and Q mixers, respectively, and
 wherein the stored processor-executable instructions are configured to cause a processor in a communication apparatus to perform operations such that applying an offset further comprises applying an offset between a bias voltage of the I Gm amplifier and a corresponding bias voltage of the Q Gm amplifier.   
     
     
         24 . The non-transitory processor-readable medium of  claim 23 , wherein the stored processor-executable instructions are configured to be executed by a processor of a communication apparatus in which the bias voltage of the I Gm amplifier comprises a common mode output voltage of the I Gm amplifier, and the bias voltage of the Q Gm amplifier comprises a common-mode output voltage of the Q Gm amplifier. 
     
     
         25 . The non-transitory processor-readable medium of  claim 15 , wherein the stored processor-executable instructions are configured to be executed by a processor of a communications apparatus that comprises a receiver comprising the I and Q signal paths, and
 wherein the stored processor-executable instructions are configured to cause a processor to perform operations further comprising:   measuring I and Q input signals coupled to the outputs of the I and Q mixers, respectively; and   adjusting the applied offset based on the measured I and Q input signals.   
     
     
         26 . The non-transitory processor-readable medium of  claim 25 , wherein adjusting the applied offset further comprises adjusting the applied offset based on a residual sideband measured from the I and Q input signals. 
     
     
         27 . The non-transitory processor-readable medium of  claim 25 , wherein the stored processor-executable instructions are configured to cause a processor to perform operations further comprising supplying a controlled input signal to the input of the receiver. 
     
     
         28 . The non-transitory processor-readable medium of  claim 27 , wherein the stored processor-executable instructions are configured to be executed by a processor of a communications apparatus that further comprises a transmitter and a duplexer, and
 wherein the stored processor-executable instructions are configured to cause a processor in a communication apparatus to perform operations such that supplying a controlled input signal further comprises:   transmitting a controlled input signal using the transmitter; and   coupling the transmitted controlled input signal to the input of the receiver via the duplexer.   
     
     
         29 . The non-transitory processor-readable medium of  claim 28 , wherein the stored processor-executable instructions are configured to cause a processor in a communication apparatus to perform operations further comprising:
 applying a plurality of candidate offsets between a bias for an element of the I signal path and a bias for an element of the Q signal path; and   measuring I and Q input signals coupled to the outputs of the I and Q mixers for each of the plurality of candidate offsets applied.   
     
     
         30 . The non-transitory processor-readable medium of  claim 29 , wherein the stored processor-executable instructions are configured to cause a processor in a communication apparatus to perform operations such that adjusting the applied offset based on the measured I and Q input signals further comprises applying the candidate offset associated with a lowest residual sideband computed from the measured I and Q input signals. 
     
     
         31 . The non-transitory processor-readable medium of  claim 12 , wherein the stored processor-executable instructions are configured to be executed by a processor of a communications apparatus that comprises a transmitter comprising the I and Q signal paths,
 wherein the I signal path comprises an I mixer and the Q signal path comprises a Q mixer, and   wherein the stored processor-executable instructions are configured to cause a processor to perform operations further comprising:   applying a reference I signal to an input of the I mixer;   applying a reference Q signal to an input of the Q mixer;   measuring a parameter of the signal transmitted by the transmitter; and   adjusting the applied offset based on the measuring the parameter of the signal transmitted by the transmitter.   
     
     
         32 . The non-transitory processor-readable medium of  claim 31 , wherein the stored processor-executable instructions are configured to be executed by a processor of a communications apparatus in which the parameter of the signal transmitted by the transmitter is a residual sideband. 
     
     
         33 . The non-transitory processor-readable medium of  claim 32 , wherein the stored processor-executable instructions are configured to be executed by a processor of a communications apparatus that further comprises a duplexer and a receiver,
 wherein the stored processor-executable instructions are configured to cause a processor in a communication apparatus to perform operations such that measuring the parameter of the signal transmitter by the transmitter further comprises coupling the signal transmitted by the transmitter to the input of the receiver via the duplexer, and wherein adjusting the applied offset further comprises applying an offset associated with a lowest residual sideband of the measured transmitted signal between a bias element for the I mixer and a bias element for the Q mixer.   
     
     
         34 . A communications apparatus for reducing mismatch between in-phase (I) and quadrature (Q) signal paths comprising:
 means for applying an offset between a bias for an element of the I signal path and a bias for an element of the Q signal path;   means for applying at least one I local oscillator signal to the I signal path; and   means for applying at least one Q local oscillator signal to the Q signal path.   
     
     
         35 . The communications apparatus of  claim 34 , further comprising means for receiving communication signals. 
     
     
         36 . The communications apparatus of  claim 34 , further comprising transmitter means for transmitting communication signals, the transmitter means comprising the I and Q signal paths. 
     
     
         37 . The communications apparatus of  claim 34 , wherein the I and Q signal paths comprise corresponding I and Q mixers, and wherein means for applying an offset further comprises means for applying an offset between a transistor in the I mixer means and a corresponding transistor in the Q mixer. 
     
     
         38 . The communications apparatus of  claim 37 , wherein means for applying an offset further comprises means for applying an offset between the gate of the transistor in the mixer means and the gate of the corresponding transistor in the Q mixer. 
     
     
         39 . The communications apparatus of  claim 37 , further comprising:
 means for applying a bias offset between a first transistor in the I mixer and a second transistor in the I mixer, the first and second transistors forming a differential pair.   
     
     
         40 . The communications apparatus of  claim 37 , wherein means for applying an offset further comprises means for applying an offset between the bulk of the transistor in the I mixer and the bulk of the corresponding transistor in the Q mixer. 
     
     
         41 . The communications apparatus of  claim 38 , wherein means for applying an offset further comprises means for applying an offset between the bulk of the transistor in the I mixer and the bulk of the corresponding transistor in the Q mixer. 
     
     
         42 . The communications apparatus of  claim 37 , wherein each mixer is a passive mixer means. 
     
     
         43 . The communications apparatus of  claim 37 , wherein each mixer is an active mixer means. 
     
     
         44 . The communications apparatus of  claim 37 , wherein each mixer is an active mixer, each active mixer comprising at least one biasing transistor, wherein means for applying an offset further comprises means for applying an offset between the bias current associated with the at least one biasing transistor in the I mixer and the at least one biasing transistor in the Q mixer. 
     
     
         45 . The communications apparatus of  claim 37 , wherein the I and Q signal paths comprise corresponding I and Q mixers and corresponding I and Q transimpedance amplifiers (TIA) coupled to the outputs of the I and Q mixers, respectively, and wherein means for applying an offset further comprises means for applying an offset between a bias voltage of the I TIAs and a corresponding bias voltage of the Q TIAs. 
     
     
         46 . The communications apparatus of  claim 45 , wherein the bias voltage of the I TIA comprises a common-mode output voltage of the I TIA, and wherein the bias voltage of the Q TIA comprises a common-mode output voltage of the Q TIA. 
     
     
         47 . The communications apparatus of  claim 34 , wherein the I and Q signal paths comprise corresponding I and Q mixers and corresponding I and Q Gm amplifiers coupled to the inputs of the I and Q mixers, respectively, and wherein means for applying an offset further comprises means for applying an offset between a bias voltage of the I Gm amplifier and a corresponding bias voltage of the Q Gm amplifier. 
     
     
         48 . The communications apparatus of  claim 47 , wherein the bias voltage of the I Gm amplifier means comprises a common-mode output voltage of the I Gm amplifier means, and
 wherein the bias voltage of the Q Gm amplifier means comprises a common-mode output voltage of the Q Gm amplifier means.   
     
     
         49 . The communications apparatus of  claim 37 , further comprising:
 a receiver comprising the I and Q signal paths;   means for measuring I and Q input signals coupled to the outputs of the I and Q mixer means, respectively; and   means for adjusting the applied offset based on the measured I and Q input signals.   
     
     
         50 . The communications apparatus of  claim 49 , wherein means for adjusting the applied offset further comprises means for adjusting the applied offset based on a residual sideband measured from the I and Q input signals. 
     
     
         51 . The communications apparatus of  claim 49 , further comprising means for supplying a controlled input signal to the input of the receiver means. 
     
     
         52 . The communications apparatus of  claim 51 , further comprising:
 a transmitter; and   a duplexer,   wherein means for supplying a controlled input signal further comprises:
 means for transmitting a controlled input signal using the transmitter; and 
 means for coupling the transmitted controlled input signal to the input of the receiver means via the duplexer. 
   
     
     
         53 . The communications apparatus of  claim 49 , further comprising:
 means for applying a plurality of candidate offsets between a bias for an element of the I signal path and a bias for an element of the Q signal path; and   means for measuring I and Q input signals coupled to the outputs of the I and Q mixer means for each of the plurality of candidate offsets applied.   
     
     
         54 . The communications apparatus of  claim 53 , wherein means for adjusting the applied offset based on the measured I and Q input signals further comprises means for applying the candidate offset associated with a lowest residual sideband computed from the measured I and Q input signals. 
     
     
         55 . The communications apparatus of  claim 34 , further comprising:
 a transmitter comprising the I and Q signal paths, wherein the I signal path comprises an I mixer and the Q signal path comprises a Q mixer;   means for applying a reference I signal to an input of the I mixer;   means for applying a reference Q signal to an input of the Q mixer;   means for measuring a parameter of the signal transmitted by the transmitter; and   means for adjusting the applied offset based on the measured parameter of the signal transmitted by the transmitter.   
     
     
         56 . The communications apparatus of  claim 55 , wherein the parameter of the signal transmitted by the transmitter is a residual sideband. 
     
     
         57 . The communications apparatus of  claim 56 , further comprising:
 a duplexer; and   a receiver,   wherein means for measuring the parameter of the signal transmitted by the transmitter means further comprises means for coupling the signal transmitted by the transmitter to the input of the receiver via the duplexer, and   wherein means for adjusting the applied offset further comprises means for applying an offset associated with a lowest residual sideband of the measured transmitted signal between a bias element for the I mixer and a bias element for the Q mixer.   
     
     
         58 . A method for reducing mismatch between in-phase (I) and quadrature (Q) signal paths in a communications system, the method comprising:
 applying an offset between a bias for an element of the I signal path and a bias for an element of the Q signal path;   applying at least one I local oscillator signal to the I signal path; and   applying at least one Q local oscillator signal to the Q signal path.