Method for improved testing of transistor arrays

Abstract

An electronic test system to evaluate the pixel and array properties of active-matrix displays that use charge or current sensitive circuits attached to the array data lines is described. Leakage-current, charging time, and other metrics can be measured for all pixels in the array without electrical or optical connection to the interior of the array. Charge or current sensitive amplifiers and selected voltage drivers may be used in conjunction with variable timing and voltages to determine individual transistor properties over an entire array in just a few seconds. Signals to be measured may be injected in several ways. Ultimately, an output signal for each pixel is measured. Thus, based on the output signal, the charging time or current, the leakage time or current, and other pixel or transistor parameters may be characterized for the entire array.

1 . A method for testing a transistor array comprising:
 selecting a first transistor row in the array to be tested;   injecting a drive voltage into a gate terminal of a second transistor row operatively connected to the first transistor row;   selectively detecting an output of the first transistor row; and, processing the output.   
     
     
         2 . The method as set forth in  claim 1  wherein the processing comprises measuring a charging time of the first transistor. 
     
     
         3 . The method as set forth in  claim 1  wherein the processing comprises measuring a discharging time of the first transistor. 
     
     
         4 . The method as set forth in  claim 1  wherein the processing comprises measuring a leakage time of the first transistor. 
     
     
         5 . The method as set forth in  claim 1  wherein the processing comprises measuring a turn-on voltage of the first transistor. 
     
     
         6 . A method for testing a transistor array comprising:
 selecting a transistor row to be tested from the array;   injecting a drive voltage into a plate terminal of the transistor;   selectively detecting an output of the transistor row; and, processing the output.   
     
     
         7 . The method as set forth in  claim 6  wherein the processing comprises measuring a charging time of the transistor. 
     
     
         8 . The method as set forth in  claim 6  wherein the processing comprises measuring a discharging time of the transistor. 
     
     
         9 . The method as set forth in  claim 6  wherein the processing comprises measuring a leakage time of the transistor. 
     
     
         10 . The method as set forth in  claim 6  wherein the processing comprises measuring a turn-on voltage of the transistor. 
     
     
         11 . The method as set forth in  claim 6  wherein the applying of the drive voltage to a plate terminal of the transistor includes applying the drive voltage to a plate disposed on the array. 
     
     
         12 . A method for testing a transistor array comprising:
 selecting a transistor row to be tested from the array;   injecting a drive voltage to charge the transistor row through selected data lines;   selectively detecting an output of the transistor row; and   processing the output.   
     
     
         13 . The method as set forth in  claim 12  wherein the processing comprises measuring a charging time of the first transistor. 
     
     
         14 . The method as set forth in  claim 12  wherein the processing comprises measuring a discharging time of the first transistor. 
     
     
         15 . The method as set forth in  claim 12  wherein the processing comprises measuring a leakage time of the first transistor. 
     
     
         16 . The method as set forth in  claim 12  wherein the processing comprises measuring a turn-on voltage of the first transistor. 
     
     
         17 . A method for testing a transistor array comprising:
 selecting a transistor row to be tested from the array;   charging the transistor row by shifting a bias level of readout circuits of the transistor row;   selectively detecting an output of the transistor row; and   processing the output.   
     
     
         18 . The method as set forth in  claim 17  wherein the processing comprises measuring a charging time of the first transistor. 
     
     
         19 . The method as set forth in  claim 17  wherein the processing comprises measuring a discharging time of the first transistor. 
     
     
         20 . The method as set forth in  claim 17  wherein the processing comprises measuring a leakage time of the first transistor. 
     
     
         21 . The method as set forth in  claim 17  wherein the processing comprises measuring a turn-on voltage of the first transistor.