Capacitor Structure

Abstract

One or more embodiments relate to a semiconductor device, comprising: a substrate; and a plurality of first conductive vias, the first conductive vias electrically coupled together, each of the first conductive vias passing through the substrate; and a plurality of second conductive vias, the second conductive vias electrically coupled together, each of the second conductive vias passing through the substrate, the second conductive vias spacedly disposed from the first conductive vias.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate; and   a plurality of first conductive vias, said first conductive vias electrically coupled together, each of said first conductive vias passing through said substrate; and   a plurality of second conductive vias, said second conductive vias electrically coupled together, each of said second conductive vias passing through said substrate, said second conductive vias spacedly disposed from said first conductive vias.   
     
     
         2 . The semiconductor device of  claim 1 , wherein said first conductive vias are staggered between said second conductive vias. 
     
     
         3 . The semiconductor device of  claim 1 , wherein said first and second conductive vias are arranged in rows and columns, said first conductive vias alternate with said second conductive vias along said rows and along said columns. 
     
     
         4 . The semiconductor device of  claim 1 , wherein said semiconductor device comprises a capacitor, said capacitor comprising a first capacitor plate spacedly disposed from a second capacitor plate, said first capacitor plate comprising said first conductive vias, said second capacitor plate comprises said second conductive vias. 
     
     
         5 . The semiconductor device of  claim 1 , wherein said first and second conductive vias comprise a metallic material. 
     
     
         6 . The device of  claim 1 , wherein the average length of said first and second conductive vias is greater than  10  times the average distance between said first conductive vias and said second conductive vias. 
     
     
         7 . The device of  claim 1 , further comprising a dielectric layer laterally surrounding each of said first and second conductive vias. 
     
     
         8 . The device of  claim 1 , wherein the material of said substrate is disposed between said first and said second conductive vias. 
     
     
         9 . The device of  claim 1 , wherein each of said second conductive vias laterally surrounds a respective one of said first conductive vias. 
     
     
         10 . A semiconductor device, comprising:
 a substrate; and   a capacitor including a first conductive plate spacedly disposed from a second conductive plate, said first conductive plate comprising a plurality of electrically coupled first conductive vias passing through said substrate, said second conductive plate comprising a plurality of electrically coupled second conductive vias passing through said substrate.   
     
     
         11 . The device of  claim 10 , wherein the material of said substrate is between said first conductive plate and said second conductive plate. 
     
     
         12 . The device of  claim 10 , wherein said first and second conductive vias comprise a metallic material. 
     
     
         13 . A capacitor structure, comprising:
 a first capacitor plate comprising a plurality of electrically coupled first conductive vias passing though a semiconductor substrate; and   a second capacitor plate spaced disposed from said first capacitor plate, said second capacitor plate comprising a plurality of electrically coupled second conductive vias passing through said substrate.   
     
     
         14 . The semiconductor device of  claim 13 , wherein said first conductive vias are disposed in a staggered arrangement between said second conductive vias. 
     
     
         15 . The semiconductor device of  claim 13 , wherein said first and second conductive vias are arranged in rows and columns, said first conductive vias alternate with said second conductive vias along said rows and along said columns. 
     
     
         16 . The semiconductor device of  claim 13 , wherein said first and second conductive vias comprise a metallic material. 
     
     
         17 . The device of  claim 13 , wherein the average length of said first and second conductive vias is greater than  10  times the average distance between the said first conductive vias and said second conductive vias. 
     
     
         18 . The device of  claim 13 , wherein the material of said substrate is disposed between said first conductive vias and said second conductive vias. 
     
     
         19 . The device of  claim 13 , wherein each of said second conductive vias laterally surrounds a respective one of said first conductive vias.