Replacement metal gate processing with reduced interlevel dielectric layer etch rate

Abstract

A semiconductor structure includes an interlevel dielectric (ILD) layer disposed over a semiconductor substrate and a transistor gate structure formed on the substrate; and a shallow gas cluster ion beam (GCIB) layer infused in a top portion of the ILD layer; wherein the GCIB layer has a slower etch rate with respect to the ILD layer.

1 . A semiconductor structure, comprising:
 an interlevel dielectric (ILD) layer disposed over a semiconductor substrate and a planarized replacement transistor gate structure formed on the substrate; and   a shallow gas cluster ion beam (GCIB) layer infused in a top portion of the ILD layer;   wherein the GOB layer has a slower etch rate with respect to the ILD layer.   
     
     
         2 . The structure of  claim 1 , wherein the ILD layer comprises an oxide layer. 
     
     
         3 . The structure of  claim 2 , wherein the transistor gate structure comprises a high-K dielectric layer and a metal gate layer. 
     
     
         4 . The structure of  claim 3 , wherein the etch rate of the GCIB is about 5 times slower than that of the ILD layer. 
     
     
         5 . The structure of  claim 4 , wherein the GCIB comprises a silicon rich oxide. 
     
     
         6 . The structure of  claim 5 , wherein the GCIB layer has a thickness of about 10 nanometers (nm) or less. 
     
     
         7 . The structure of  claim 6 , wherein the ILD layer has a thickness of about 40 nm. 
     
     
         8 . The structure of  claim 1 , further comprising a channel region defined in the semiconductor substrate, below the planarized replacement transistor gate structure, wherein the channel region is free from ions of the shallow GCIB layer infused in the top portion of the ILD layer.