Atomic Layer Deposition of Hafnium and Zirconium Oxides for Memory Applications
Abstract
Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal-rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A resistive switching memory element comprising:
a first electrode; and a metal oxide film stack disposed over the first electrode; wherein the metal oxide film stack comprises a metal oxide buffer layer and a metal oxide bulk layer, wherein the metal oxide buffer layer is disposed between the metal oxide bulk layer and the first electrode.
wherein the metal oxide bulk layer comprises MO x ;
wherein M is hafnium or zirconium and x is within a range from about 1.65 to about 1.95; wherein the metal oxide buffer layer comprises M′O 2 ; and wherein M′ is zirconium if M is hafnium or M′ is hafnium if M is zirconium.
2 . The resistive switching memory element of claim 1 , wherein the metal oxide bulk layer comprises HfO x , where x is within a range from about 1.70 to about 1.90, and wherein the metal oxide buffer layer comprises ZrO 2 .
3 . The resistive switching memory element of claim 2 , wherein the metal oxide bulk layer has a thickness within a range from about 15 Å to about 50 Å, and wherein the metal oxide buffer layer has a thickness within a range from about 5 Å to about 15 Å.
4 . The resistive switching memory element of claim 1 , wherein the metal oxide bulk layer comprises ZrO x , where x is within a range from about 1.70 to about 1.90, and wherein the metal oxide buffer layer comprises HfO 2 .
5 . The resistive switching memory element of claim 4 , wherein the metal oxide bulk layer has a thickness within a range from about 15 Å to about 50 Å, and wherein the metal oxide buffer layer has a thickness within a range from about 5 Å to about 15 Å.
6 . The resistive switching memory element of claim 1 , wherein the metal oxide buffer layer is less electrically resistive than the metal oxide bulk layer.
7 . The resistive switching memory element of claim 1 , wherein the metal oxide buffer layer further comprises a dopant.
8 . The resistive switching memory element of claim 7 , wherein the dopant is hafnium oxide if M′ is zirconium or the dopant is zirconium oxide if M′ is hafnium.
9 . The resistive switching memory element of claim 7 , wherein the dopant is zirconium oxide and M′ is hafnium, and wherein a concentration of zirconium oxide in the metal oxide buffer layer is between about 0.25% atomic and 25% atomic.
10 . The resistive switching memory element of claim 7 , wherein the dopant is zirconium oxide and M′ is hafnium, and wherein a concentration of zirconium oxide in the metal oxide buffer layer is between about 1% atomic and 15% atomic.
11 . The resistive switching memory element of claim 7 , wherein the dopant is hafnium oxide and M′ is zirconium, and wherein a concentration of hafnium oxide in the metal oxide buffer layer is between about 0.25% atomic and 25% atomic.
12 . The resistive switching memory element of claim 7 , wherein the dopant is hafnium oxide and M′ is zirconium, and wherein a concentration of hafnium oxide in the metal oxide buffer layer is between about 1% atomic and 15% atomic.
13 . The resistive switching memory element of claim 7 , wherein the metal oxide buffer layer has a thickness of between 2 Å and 80 Å.
14 . The resistive switching memory element of claim 1 , wherein the metal oxide buffer layer is a laminate comprising one or more layers of M′O 2 and one or more layers of MO 2 .
15 . The resistive switching memory element of claim 1 , wherein the metal oxide bulk layer is a laminate comprising one or more layers of M′O 2 and one or more layers of MO x .
16 . The resistive switching memory element of claim 1 , further comprising a silicon oxide layer and a second electrode;
wherein the silicon oxide layer, the metal oxide bulk layer, and the metal oxide buffer layer are disposed between the first electrode and the second electrode; and wherein the silicon oxide layer is disposed between the second electrode and the metal oxide bulk layer.
17 . The resistive switching memory element of claim 16 , wherein the silicon oxide layer has a thickness of between about 2 Å and 40 Å.
18 . The resistive switching memory element of claim 1 , wherein x is within a range from about 1.70 to about 1.90.
19 . The resistive switching memory element of claim 1 , wherein x is within a range from about 1.75 to about 1.85.
20 . A resistive switching memory element comprising:
a first electrode; a metal oxide buffer layer; and a metal oxide bulk layer; wherein the metal oxide buffer layer is disposed between the metal oxide bulk layer and the first electrode; wherein the metal oxide bulk layer comprises HfO x ; wherein x is within a range from about 1.65 to about 1.95; and wherein the metal oxide buffer layer comprises ZrO 2 .Join the waitlist — get patent alerts
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