Semiconductor Constructions and Assemblies and Electronic Systems

Abstract

The invention includes semiconductor assemblies having two or more dies. An exemplary assembly has circuitry associated with a first die front side electrically connected to circuitry associated with a second die front side. The front side of the second die is adjacent a back side of the first die, and a through wafer interconnect extends through the first die. The through wafer interconnect includes a conductive liner within a via extending through the first die. The conductive liner narrows the via, and the narrowed via is filled with insulative material. The invention also includes methods of forming semiconductor assemblies having two or more dies; and includes electronic systems containing assemblies with two or more dies.

1 . A method of forming a construction, comprising:
 providing a semiconductor die having a front side with circuitry associated therewith, having a back side in opposing relation to the front side, having an electrically conductive material pad;   forming at least one via extending through the die from the front side toward the back side and at least partially through a base semiconductor material of the die;   forming a liner of insulative material lining the via where the insulative material does not extend over the electrically conductive material pad;   forming an electrically insulative material within the via; and   forming a conductive liner within the via over the liner of insulative material and extending over the electrically conductive material pad prior to forming the electrically insulative material within the via, the conductive liner narrowing the via.   
     
     
         2 . The method of  claim 1  wherein the semiconductor die is a first semiconductor die, and further comprising:
 removing material from the back side of the first semiconductor die to expose the conductive liner. 
 
     
     
         3 . The method of  claim 2  further comprising:
 providing a second semiconductor die stacked face to back side of the first die having a second front side with circuitry associated therewith; and 
 electrically interconnecting said at least some of the circuitry associated with the front side of the first die with circuitry associated with the second front side through the conductive liner via a solder ball that contacts the conductive liner. 
 
     
     
         4 . A method of forming a semiconductor assembly, comprising:
 providing a first wafer comprising a plurality of first semiconductor dies having pads of electrically conductive material; the first dies having first front sides, and first back sides in opposing relation to the first front sides;   forming vias extending through the first front sides and into the first dies;   forming liners of insulative material lining the vias, where the insulative material does not extend over the electrically conductive material of the pads.   
     
     
         5 . The method of  claim 4  further comprising:
 forming conductive liners within the vias over the liners of insulative material and extending over the electrically conductive material of the pads; 
 filling the lined vias with electrically insulative material; 
 exposing segments of the conductive liners along a backside of the conductive liners; 
 providing second semiconductor dies having second front sides stacked face to first back side of the first dies having first front sides; and 
 providing electrical interconnects extending from the second front sides to the exposed segments of the conductive liners utilizing solder balls. 
 
     
     
         6 . The method of  claim 5  wherein the second semiconductor dies are provided as singulated dies. 
     
     
         7 . The method of  claim 5  wherein the second semiconductor dies are together provided as a second wafer; and wherein the singulating singulates the second semiconductor dies from the second wafer. 
     
     
         8 . The method of  claim 5  wherein singulating of the first semiconductor dies occurs after the providing of the electrical interconnects. 
     
     
         9 . The method of  claim 5  wherein singulating of the first semiconductor dies occurs before the providing of the electrical interconnects. 
     
     
         10 . The method of  claim 5  further comprising encapsulating outer surfaces of the first and second dies prior to the singulating of the first semiconductor dies. 
     
     
         11 . A method of forming a semiconductor assembly, comprising:
 providing a semiconductor wafer having a primary die region; the wafer having a first front side, and having a first back side in opposing relation to the first front side;   forming a via within the primary die region and extending through the first front side, through an electrically conductive material pad and into a first die;   forming a liner of insulative material lining the via, where the insulative material does not extend over the electrically conductive material of the pad;   forming a conductive liner within the via over the liner of insulative material and extending over the electrically conductive material of the pad.   
     
     
         12 . The method of  claim 11  further comprising:
 connecting solder balls to the first front side; 
 forming a dammed region around a periphery of the first front side, and flowing filler material within the dammed region to cover the first front side between the solder balls and fill the via; 
 curing the filler material into a substantially solid electrically insulative material within the via and over the first front side; 
 providing a secondary semiconductor die having a second front side stacked front to first back side with the first die; and 
 providing an electrical interconnect extending from the second front side to the exposed segment of the conductive liner utilizing a solder ball. 
 
     
     
         13 . The method of  claim 12  wherein the flowing of the relatively low viscosity material is conducted at a first temperature and the curing of the relatively low viscosity material comprises changing the temperature to a second temperature. 
     
     
         14 . The method of  claim 12  further comprising, after the flowing of the relatively low viscosity material and prior to the curing of the relatively low viscosity material, performing at least one sequence of exposure of the relatively low viscosity material to changing pressure to assist the flow of the relatively low viscosity material into the via. 
     
     
         15 . The method of  claim 12  wherein the solder balls are first solder balls, and wherein the electrical interconnect comprises a second solder ball.