Semiconductor component with vertical structures having a high aspect ratio and method

Abstract

A semiconductor component with vertical structures having a high aspect ratio and method. In one embodiment, a drift zone is arranged between a first and a second component zone. A drift control zone is arranged adjacent to the drift zone in a first direction. A dielectric layer is arranged between the drift zone and the drift control zone wherein the drift zone has a varying doping and/or a varying material composition at least in sections proceeding from the dielectric.

What is claimed is: 
     
         1 . A method for producing a semiconductor component comprising:
 providing a semiconductor body having a first side, into which a trench extends proceeding from the first side;   conformally depositing at least one semiconductor layer at least on the sidewalls of the trench; and   producing a dielectric layer on the semiconductor layer in a trench remaining after the production of the semiconductor layer.   
     
     
         2 . The method of  claim 1 , comprising producing the semiconductor layer such that it has a varying doping. 
     
     
         3 . The method of  claim 2 , comprising forming the at least one semiconductor layer such that a doping concentration of the semiconductor layer changes continuously in a direction of the dielectric layer until an extremum is reached, wherein the extremum is reached at a distance from the dielectric layer, and changes continuously in a direction of the dielectric layer proceeding from the extremum. 
     
     
         5 . The method of  claim 1 , comprising forming the at least one semiconductor layer with a doping that is complementary to a doping of the semiconductor body along sidewalls of the trench. 
     
     
         6 . The method of  claim 1 , comprising producing the semiconductor layer such that it has a varying material composition. 
     
     
         7 . The method of  claim 1 , comprising composing the semiconductor layer at least partly of silicon-germanium. 
     
     
         8 . The method of  claim 7 , comprising forming the at least one semiconductor layer such that a germanium content decreases in a direction of the dielectric layer. 
     
     
         9 . The method of  claim 7 , wherein forming the at least one semiconductor layer comprises:
 forming a first layer composed of Si x Ge 1-x , where 0.7<x≦1; and   forming on the first layer a second layer composed of silicon or Si y Ge 1-y  where 0.7<y≦1 and x<y.   
     
     
         10 . The method of  claim 7 , wherein forming the at least one semiconductor layer comprises:
 forming a first layer composed of silicon or Si x Ge 1-x , where 0.7<x≦1; and   forming on the first layer a second layer of Si y Ge 1-y  where 0.7<y≦1 and x>y.   
     
     
         11 . The method of  claim 1 , comprising producing the dielectric layer by a thermal oxidation. 
     
     
         12 . The method of  claim 11 , comprising closing the trench by the thermal oxidation. 
     
     
         13 . The method of  claim 1 , comprising depositing a semiconductor layer on the semiconductor body in such a way that the trench in the region of the front side is overgrown by the semiconductor layer, such that a cavity remains in the region of the original trench. 
     
     
         14 . The method of  claim 13 , comprising opening the cavity by etching back on the front side. 
     
     
         15 . The method of  claim 1 , comprising forming the dielectric layer with a thickness of 50 nm to 140 nm. 
     
     
         16 . The method of  claim 1 , comprising forming the dielectric layer with a thickness of 50 nm to 140 nm. 
     
     
         17 . The semiconductor component of  claim 1 , comprising forming the dielectric layer with a thickness of 30 nm to 200 nm.